Using Contrapositive Law to Enhance Implication Graphs of Logic Circuits

1. Using Contrapositive Law to Enhance Implication Graphs of Logic Circuits Kunal K Dave Master’s Thesis Electrical & Computer Engineering Rutgers University 4/23/2004

2. Talk Outline • Background • Oring Nodes • New Algorithms • Results • Conclusion and Future Work Kunal Dave - Dept. of ECE

3. Background • Implication graph-based ATPG techniques: • Larrabee et al. -- IEEE-TCAD, 1992 • Chakradhar et al.-- IEEE-TCAD, 1993 • Tafershofer et al. -- IEEE-TCAD, 2000 • Implication based fault-independent redundancy identification techniques: • Iyer and Abramovici – IEEE-VLSI Systems, 1996 • Agrawal et al. -- ATS, 1996 • Gaur et al. -- DELTA, 2002 • Mehta et al. -- VLSI Design, 2003 Kunal Dave - Dept. of ECE

4. a c b Boolean false function* AND:ab c = 0 ac + bc + abc = 0 a c b Λ1 Λ3 c a b Λ2 Implication Graph • An implication graph (IG)  Digital circuit in the form of a set of binary and higher-order relations. Boolean equation AND:c = ab * Chakradhar et al. -- IEEE-D&T, 1990 Kunal Dave - Dept. of ECE

5. a s b b Osa Osb Os b Oa Oc Λ1 Λ3 b Os Osa Oc Osb Oa Λ2 Observability Implications Oc Oa Observability nodes – Agrawal, Lin and Bushnell -- ATS, 1996 Kunal Dave - Dept. of ECE

6. Redundancy Identification • Obtain an implication graph from the circuit topology and compute transitive closure. • There are 8 different conditions on the basis of which a fault is said to be redundant.* • Examples: • If node c implies c then s-a-0 fault on line c is redundant. • If node Oc implies Oc then c is unobservable and both s-a-0 and s-a-1 faults on line c are redundant. * Agrawal et al. -- ATS, 1996 & Gaur et al. -- DELTA, 2002 Kunal Dave - Dept. of ECE

7. Motivation – Problem Statement • Implication graph (IG)  Digital circuit represented as a set of binary and higher-order relations. • Binary relations  full implication edges. • Higher-order relations  partial implications using anding nodes. • Incomplete representation, can be improved. • An improvement--use contrapositive rule to derive new partial implication nodes, oring nodes, to incorporate more complete logic information in the implication graph. Kunal Dave - Dept. of ECE

8. Contrapositive a c c a c b Contrapositive b c Oring Nodes Expansion of Boolean false function AND :ac + bc + abc = 0 De-Morgan Contrapositive (a Λb) c c (b V c) c (b V c) De-Morgan Contrapositive (a Λc) b b (a V c) b (a V c) De-Morgan Contrapositive (b Λc) a a (b V c) a (b V c) Kunal Dave - Dept. of ECE

9. Use of Oring Nodes a c b d a c d b Λ2 Λ1 a c d b V1 V2 Kunal Dave - Dept. of ECE

10. Extended Use of Oring Node s-a-0 a c b e d Oac b a Λ1 V1 d Oc b Λ2 a Kunal Dave - Dept. of ECE

11. Motivation - A Problem Statement • Addition of a new edge can change the transitive closure (TC). • Re-computation of TC is required. • Algorithms are needed to update TC rather than re-computing it. • Develop new algorithms that dynamically update the transitive closure graph while extracting implications from a logic network. • Apply new implication graph and new dynamic update algorithms to redundancy identification to obtain better performances. Kunal Dave - Dept. of ECE

12. Update routine (1) Update(G, vs, vn){ (2) for each parent Piof source vs{ (3) for each child Cjof destination vn{ (4) if (edge Pi Cj does not exist) (5) addTcEdge(Pi, Cj); (6) } } }//Update a b c d Kunal Dave - Dept. of ECE

13. Update_Partial_A • Converts partial implications in to possible full implications using anding nodes. • New edge, vs vd, added??? • Check if vdis aparent of an anding node Λx. • Find a common grandparent Gp of the node Λx. • Add TC edge from Gp to successor(Λx). c e a Λ1 d Kunal Dave - Dept. of ECE

14. Update_Partial_AO • Converts partial implications in to possible full implications using oring nodes. • New edge, vs vd, added??? • Check if vsis achild of an oring node Vx. • Find a common grandchild Gc of the node Vx. • Add TC edge from predecessor(Vx) to Gc. c e a V1 d Kunal Dave - Dept. of ECE

15. Update_Partial_AO (contd…) • Also obtains backward partial implications using oring nodes that were previously obtained by extra anding nodes. s-a-0 a c b Oac b e d a Λ1 Oc d V1 b Λ2 a Kunal Dave - Dept. of ECE

16. a n w x p c z n An Example m b Λ1 V1 m Kunal Dave - Dept. of ECE

17. Number of Partial Nodes Kunal Dave - Dept. of ECE

18. Results on ISCAS Circuits Kunal Dave - Dept. of ECE

19. ISCAS ’85 -- C1908 Redundant faults 949 952 s-a-1 979 953 887 s-a-1 926 74 Kunal Dave - Dept. of ECE

20. ISCAS ’85 -- C5315 Redundant fault PI 1 0 0 0/1 0/1 1 1 PI 1 0/1 0/1 PO 0 0 0 1 1 1 1 1 Kunal Dave - Dept. of ECE

21. ISCAS ’85 -- C5315 Redundant fault PI 1 0/1 0/1 0/1 1 PI 0 0 0/1 PO 1 1 1 0 1 0 0 1 Kunal Dave - Dept. of ECE

22. Conclusion – Future Work • Contributions of thesis • New partial implication structure called oringnode enhances implication graph of logic circuits; more complete and more compact the the graph with just anding nodes. • New algorithms dynamically update the transitive closure every time a new implication edge is added; greater efficiency over complete recomputation. • New and improved fault-independent redundancy identification. • New techniques can be further explored in following areas: • Fanout stem unobservability – proposed solution • Equivalence checking • Test generation Kunal Dave - Dept. of ECE

23. ThankYou Kunal Dave - Dept. of ECE