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Instruction Encoding

Instruction Encoding. Thorne : Chapter 13.2, Appendix V.B Additional notes in : Instruction Encoding Note. Instruction Encoding. On the Intel 8086, an instruction is a sequence of 1..6 bytes A simple (and incomplete) model of an instruction is as follows :. Byte 1. Byte 2. Byte 3.

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Instruction Encoding

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  1. Instruction Encoding • Thorne : Chapter 13.2, Appendix V.B • Additional notes in : Instruction Encoding Note SYSC3006

  2. Instruction Encoding On the Intel 8086, an instruction is a sequence of 1..6 bytes • A simple (and incomplete) model of an instruction is as follows : Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Opcode Operand Operand Operand Operand Operand Tells what kind of instruction, How many bytes… Source if needed Destination Operand, if needed SYSC3006

  3. Number of Bytes Depends on … Number ofOperands NOP INC BX (Thorne, p 668) ADD BX, 1 (Thorne, p 667) … 1001 0000 0100 0001 1000 0011 1100 0011 0000 0001 0000 0000 Immediate value: a word (little endian) SYSC3006

  4. Number of Bytes Depends on … Addressing Modes BX | AX 00000001 11000011 ADD BX, AX ADD BX, 1 ADD BL, 1 ADD BX, [1] ADD BL, [1] Register Immediate 10000001 11000011 00000001 00000000 Register Immediate 10000000 11000011 00000001 Register Direct 00000011 00011110 00000001 00000000 Register Direct 00000010 00011110 00000001 00000000 SYSC3006

  5. Review Earlier Slides on Addressing Modes • Register mode : operand is a register • Immediate mode : operand is a constant • Constant value is encoding as part of instruction • value is hard-coded (static) • Constant value is loaded into IR during fetch • Constant value obtained from IR during execution 3) Direct memory mode : operand is address offset of memory variable • Constant address offset is encoded as part of instruction • Address offset is hard-coded (static) although contents of address may be dynamic • During execution, the address offset is implicitly combined with DS SYSC3006

  6. Indirect Addressing Modes Number of Bytes Depends on … Addressing Modes Assume : WORD PTR Indirect Immediate ADD [BX], 1 ADD [BX+2], 1 ADD [BX+SI], 1 ADD [BX+SI+2], 1 10000001 00000111 00000001 00000000 Immediate Based Constant 10000001 01000111 00000010 00000001 00000000 Immediate Base-Index 10000001 00000000 00000001 00000000 Immediate Base-Index with Constant 10000001 01000000 00000010 00000001 00000000 SYSC3006

  7. Review Earlier Slides on Addressing Modes [BX] [BX+2] • Indirect: Operand is an address offset held in a register • Based or Indexed Indirect : Operand is an address offset held in a register and a constant offset • During fetch, constant offset is read in as part of instruction • During execution, CPU uses temporary register to calculate BX + constant • It then accesses memory addressed by BX + constant 3) Base-Index : Operand is an address offset held in two register • During execution, CPU calculates sum of 2 registers • It then accesses memory addressed by sum 4) Base-Index with Displacement : Like based-indexed mode, except includes a constant too • During execution, CPU calculates sum of 3 values • It then accesses memory addressed by sum [BX+SI] [BX+SI+2] SYSC3006

  8. Instruction Encoding : J* • On all jump instructions, the target must supply a value that will be used to modify the IP • Absolute addressing (Assembly code): The instruction contains a 16-bit constant value to replace the IP Execution Semantics: IP := new value • Relative addressing (Machine code): : The instruction contains a value to be added to IP (after the fetch!) Execution Semantics : IP := IP + value If the value is positive, the jump is “forward” If the value is negative, the jump is “negative” • Register/memory indirect addressing: The instruction specifies a register or memory location that contains the value to be used to replace IP     Execution Semantics : IP := mem[addrs]     IP := register SYSC3006

  9. Specifying Control Flow Targets (Intra-segment) Question : What addressing modes is used below ? JMP 1000h JMP here SYSC3006

  10. JMP target Unconditional JUMP • Control is always transferred to specified (relative) target. Relative Addressing Example: .LST file fragment address machine instruction ASM instruction (memory contents) 0034H E9 10 02 JMP here 0037H …. …. …. …. …. 0247 here: start of fetch: IP = 0034H IR = ???????? after fetch: IP = 0037H IR = E9 10 02 after execute: IP = 0247H IR = E9 10 02 Relative addressing = JMP 247 Absolute addressing (Little endian=0210h) SYSC3006

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