Exemplar ™ Logic: High Level Synthesis Solutions for FPGA Design

1. Exemplar™ Logic: High Level Synthesis Solutions for FPGA Design Introduction to High Level Synthesis Software EE690 Presentation Sanjeev Gunawardena March 17th 1998

2. Exemplar™ Logic Synthesis Environment • VHDL Discovery Kit • Low end VHDL only synthesis environment. • Leonardo • Provides open and interactive synthesis environment for more aggressive designs. • User has complete control of design hierarchy and is able to dissolve, merge, preserve and flatten blocks on an individual basis. • Full constraint-based timing optimization. • Dual ASIC and FPGA/CPLD output through a single design flow. • Gallileo • Comprehensive VHDL and Verilog HDL support. • Supports high density FPGA and CPLD devices. • Broad FPGA and CPLD technology support. • Third party simulation with Model Technology and Cadence Verilog-XL.

3. Leonardo™ with Extreme Technology - Features • ASIC, FPGA, and CPLD optimization • Mixed Verilog, VHDL and EDIF synthesis • Design re-use with FPGA and ASIC device retargeting • Novice and expert modes of operation • Constraint-based timing optimization • Hierarchy manipulation • Hierarchical design browser • RAM and counter inferencing • Constraint-based static timing analysis • Schematic viewer with critical path highlighting • Open and interactive design environment • Support for EDIF, XNF, VHDL, and Verilog netlists • Node-locked and floating licenses on heterogenous platforms • Windows and Unix support

4. Leonardo™ with Extreme Technology - Quality of results • FAST (FPGA Architecture Specific Technology) Optimization. • Optimization algorithms and settings are selected based on area and timing goals, and the target technology. • F.A.S.T. enables Leonardo to eliminate unnecessary and unproductive optimizations.

5. Leonardo™ with Extreme Technology - Quality of results • RAM Inference from RTL • Synchronous and asynchronous technology-specific RAMs are automatically inferred from a 2-dimensional array. • Eliminates the need to hand instantiate while maintaining code portability.

6. Leonardo™ with Extreme Technology - Quality of results • Module Generation • High-level design requires the use of operators such as add,subtract, multiply, compare and increment. • These functions may be inefficient to synthesize as random logic. • An ideal implementation for the technology is generally already known. • Leonardo’s Module Generation (MODGEN) automatically detects many common arithmetic relational and other data flow operations and uses a technology-specific implementation. • Reduces synthesis time and improves results. • Module generators are optimized for different architectures and include area and delay trade-offs.

7. Leonardo™ with Extreme Technology - Quality of results • Extensive HDL Language Support • Verilog IEEE1364-1995 • VHDL IEEE 1076-1993 and VHDL IEEE 1164 • Supported VHDL constructs • configuration • declaration statements • multi-dimensional arrays • recursive functions • record types

8. Leonardo™ with Extreme Technology - Advanced Functionality • Constraint Based Timing Optimization • Provides additional timing gains once the primary optimization has completed. • Users can apply timing and loading constraints to the input and output ports of hierarchical blocks. • Leonardo’s timing optimization engine will identify and optimize all critical paths within a block.

9. Leonardo™ with Extreme Technology - Advanced Functionality • Hierarchy Manipulation • Leonardo supports complete hierarchy manipulation. • Hierarchy can be preserved throughout the optimization process. • The “group” command can be used to combine two or more hierarchical blocks into a single block. • The “ungroup” command can be used to selectively dissolve individual blocks of hierarchy.

10. Leonardo™ with Extreme Technology - Advanced Functionality • ASIC Optimization • State of the art area and timing optimization algorithms (based on UC-Berkley’s MIS algorithms) combined with Exemplar’s new Extreme optimization technology makes Leonardo the fastest and most productive ASIC synthesis tool on the market today. • Advanced timing analysis employs lookup table based non-linear delay models to accurately predict pre-layout delays for deep sub-micron ASIC technologies. • SDF (back annotation) is supported for post- layout timing analysis. • Leonardo is supported by many leading ASIC vendors worldwide. • Leonardo’s ASIC capabilities make it the only synthesis tool in the market today to support dual ASIC and FPGA/CPLD flows from within a single High Level Design environment.

11. Leonardo™ with Extreme Technology - User Interface • Leonardo’s graphical user interface is designed to simplify the process of interactive synthesis. • Technology-specific flow guides easily guide new users through the design process • Leonardo’s main window provides pull-down menu and command line access to commands • The Design Hierarchy Browser simplifies the process of bottom-up and interactive design. Sub-blocks can be easily separated out for individual optimization. The design browser assists in all hierarchy manipulation commands such as group and ungroup.

12. Leonardo™ with Extreme Technology - Modes of Operation • Leonardo can be run in three different modes of operation to suit all preferences and needs; 1) Leonardo GUI Provides easy access to the Leonardo command set through pull-down menus and the Design Hierarchy Browser. Results can be viewed using Leonardo’s schematic viewer. 2) Galileo Extreme For users new to synthesis or anyone who desires a simple 3-step synthesis process, Leonardo may be invoked as Galileo Extreme. 3) Leonardo Batch For users familiar with the Leonardo command set who prefer to drive synthesis and optimization runs through a command line interface or from scripts.

13. Leonardo™ with Extreme Technology - Supported ASICs and FPGAs • ASICs • More than 60 ASIC libraries from over 25 vendors. • FPGAs and CPLDs • Actel ACT1, ACT2, ACT3, 1200XL, 3200DX • Atmel 6K02, 6K04 • Altera MAX5000, MAX7000, MAX9000,FLEX 6000, FLEX 8000, FLEX10K • Cypress C340, C370, C380 • Lattice pLSI • Lucent Technologies 3000, ORCA 1C, 2C, 2CA, 2TA • Motorola MPA 1000, MPA 2000 • QuickLogic pASIC1, pASIC2 • Xilinx 3000, 3000A, 3000L, 3100, 3100A, 4000, XC3000, XC4000, XC4000E, XC4000EX, XC4000L, XC4000XL, XC5200, XC7200A, XC7300, XC9500

14. Product Comparison Table

15. Product Comparison Table

16. Installation - Current Status • I was unable to successfully install the Exemplar Logic tools in Rm. 301; hope to resolve this problem this week and have Leonardo ready for Spring quarter. • I hope to prepare some lab exercises using the Leonardo synthesis environment and target designs to the Xilinx 4000 FPGA. These labs will probably be included in EE416/516: VLSI Design II. • Leonardo is a far superior tool compared to AutoLogic ll. As such, it will replace AutoLogic II in VLSI lab in most cases. • Licenses for PCs will be available shortly under the Mentor Graphics university program. The possibility of installing Leonardo in the FPGA lab PCs will be explored when these licences become available.

17. Summary • To summarize, I would like to show a presentation of Leonardo and Gallileo included in Exemplar’s demo CD.

18. Acknowledgments • The bulk of the material for this presentation was obtained from the Exemplar CD ROM and Exemplar WWW site at http://www.exemplar.com