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References: F. Maloberti Analog Design for CMOS VLSI Systems Kluwer 2001 J. Millman, C. Halkias

References: F. Maloberti Analog Design for CMOS VLSI Systems Kluwer 2001 J. Millman, C. Halkias Integrated Electronics: Analog and Digital Circuit and Systems McGraw-Hill 1972 R. Spencer, M. Ghausi Introduction to Electronic Circuit Design Prentice Hall 2003 P. Gray, R Meyer

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References: F. Maloberti Analog Design for CMOS VLSI Systems Kluwer 2001 J. Millman, C. Halkias

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  1. References: F. Maloberti Analog Design for CMOS VLSI Systems Kluwer 2001 J. Millman, C. Halkias Integrated Electronics: Analog and Digital Circuit and Systems McGraw-Hill 1972 R. Spencer, M. Ghausi Introduction to Electronic Circuit Design Prentice Hall 2003 P. Gray, R Meyer Analysis and Design of Analog Integrated Circuits (3rd ed.) Wiley 1993 M.S. Tyagi Introduction to Semiconductor Material and Devices Wiley 1991

  2. MATERIALS: electric behavior semiconductor Insulator conductor

  3. MATERIALI: comportamento elettrico L’ultima banda riempita di elettroni si definisce banda di valenza. La prima banda lasciata vuota si definisce invece banda di conduzione. L'intervallo di energie fra la banda di valenza e quella di conduzione si definisce banda proibita (band gap). Un sistema in cui gli ultimi elettroni hanno la possibilità di spostarsi in livelli energetici molto vicini, infinitesimamente più alti in energia, cioè hanno mobilità elevata è un buon conduttore di elettricità.

  4. SEMICONDUCTORS: electric behavior Fermi-Dirac distribution: occupation probability for the energy level E In semiconductors EF is in the Band-Gap

  5. SEMICONDUTTORI intrinseci: Portatori liberi in cui N(E) rappresenta la densità degli stati energetici in un dato materiale. NC è il numero degli stati disponibili (per cm-3) in banda di conduzione

  6. DOPING ACCEPTOR DONOR EF n-type T effect The Fermi energy moves with doping EF p-type

  7. Materials: Si substrate • Monocrystalline silicon is produced from purified polycrystalline silicon by “pulling” an ingot • polysilicon is melted using radio frequency induction heaters • “seed crystal” of monocrystalline silicon is dipped into melt • silicon grows around structure of seed as seed is slowly withdrawn • Sawed into wafers about 600 microns thick • only a few microns are actually used for IC devices • then etched, polished, and cleaned • stacked in carriers

  8. Also PVD

  9. Materials • Single crystal silicon – SCS • Anisotropic crystal • Semiconductor, great heat conductor • Silicon dioxide is created by interaction between silicon and oxygen or water vapor • Si + O2 = SiO2 or Si + 2H2O = SiO2 + 2H2 • Excellent thermal and electrical insulator • protects surface from contaminants • forms insulating layer between conductors • forms barrier to dopants during diffusion or ion implantation • grows above and into silicon surface • Thermal oxide, LTO, PSG: different names for different deposition conditions and methods • Polycrystalline silicon – polysilicon • Mostly isotropic material • Semiconductor • also a conductor, but with much more resistance than metal or diffused layers • created when silicon is epitaxially grown on SiO2 • commonly used (heavily doped) for gate connections in most MOS processes • Silicon nitride – Si3N4 • Excellent electrical insulator • Aluminum – Al • Metal – excellent thermal and electrical conductor

  10. PHOTOLITOGRAPHY Thick film: 1 mm Photoresist spin.-coating Uv - X-ray EXPOSITION: The mask is transferred to the photoresist

  11. The photoresist chemically reacts and dissolves in the developing solution, only on the parts that were not masked during exposure (positive method). • Development is performed with an alkaline developing solution. • After the development, photoresist is left on the wafer surface in the shape of the mask pattern. Masked photoresist • solvents remove exposed (unexposed) resist • Etching removes material from wafer surface where resist has been removed

  12. Dry etching Wet etching

  13. EFFECT OF FLATBAND VOLTAGE VFB (VFB < 0)

  14. VGB = 0

  15. SUBSTRATE P-type Si SUBSTRATE CONTACT Polisilicon OXIDE SiO2 GATE Polisilicon VGB VOX -VFB - - + Space charge regions x xD -tOX 0 Potential VGB-VFB VOX Φs(0) x xD -tOX 0

  16. STRONG INVERSION CONDITION

  17. SMALL SIGNAL EQUIVALENT CIRCUIT OF A MOS TRANSISTOR

  18. MOSTRANSISTOR LAYOUT • SOURCE AND DRAIN PARASITIC RESISTANCES • SOURCE AND DRAINPARASITIC CAPACITANCES • MATCHING

  19. SOURCE AND DRAINPARASITIC RESISTANCES

  20. SOURCE AND DRAINPARASITIC CAPACITANCES

  21. MATCHING You must avoid: D S S D Use always the same MOS orientation in your layout: silicon is anisotropic

  22. MATCHING 1 2 3

  23. MATCHING 1 2 3

  24. MATCHING

  25. DESIGN RULES Geometrical recommendations due to the limited accuracy of the technology (mask alignment, lateral diffusion, etching undercut, optical resolution…) Design Kit: design rules + Spice models and technology features

  26. INTEGRATED RESISTORS 1

  27. INTEGRATED RESISTORS 2 DIFFERENT SOLUTIONS (a)

  28. INTEGRATED RESISTORS 3 DIFFERENT SOLUTIONS (b) • POLYSILICON RESISTORS • Lower coupling with substrate • Up to two shieldings • Top shielding (from noisy metal lines, package coupling….)

  29. INTEGRATED RESISTORS 3

  30. INTEGRATED RESISTORS 4 FACTORS AFFECTING ACCURACY • Poor absolute accuracy (20-40% - large parameter drift) • Good matching (ratio) accuracy (0.1-0.2% - it depends on local parameter variations)

  31. INTEGRATED RESISTORS 5 Design Guidelines (a)

  32. INTEGRATED RESISTORS 6 Design Guidelines (b)

  33. INTEGRATED RESISTORS 7 Design Guidelines (c)

  34. INTEGRATED CAPACITORS

  35. INTEGRATED CAPACITORS

  36. INTEGRATED CAPACITORS tox ≤ 10 nm εr(SiO2)=3.8 COX ~ 3.36 fF/μm2 COX

  37. INTEGRATED CAPACITORS

  38. INTEGRATED CAPACITORS

  39. INTEGRATED CAPACITORS • A’ = W’L’= WL – 2 (L+W)Δx = A – P Δx = A (1 - Δx P/A) • The relative reduction of A is constant, given Δx, if the ratio P/A is kept constant (same P/A for matched elements) • Boundary mismatch • The reduction of the capacitance due to the fringe effect is proportional to tox P/A -> (L, W >> tox) (additional source of error) • Thick oxide capacitance contribution (additional source of errors)

  40. INTEGRATED CAPACITORS Layout examples for poly1-poly2 capacitors

  41. INTEGRATED CAPACITORS Matching: common centroid structures Schielding (well)

  42. INTEGRATED CAPACITORS Matching: capacitors with non integer ratio [C2/C1] [C2/C1] squared C1capacitors with area L2 1 rectangular Ck capacitor with area Wk Lk =C2/C1- P/A constant for all the capacitors L2/4L=L/4=LkWk/2(Lk + Wk) Ck/C1=LkWk/L2

  43. INTEGRATED CAPACITORS – Layout Guidelines for Matching

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