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Instruction Classification and Addressing Mode

Instruction Classification and Addressing Mode. 计算机学院 李征 Tel ： 13882153765 Email ： lizheng@cs.scu.edu.cn OICQ: 1340915. Assembler and Machine Instruction. In principle, assembler instruction correspond with machine instruction one by one. However, there are few exceptions.

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Instruction Classification and Addressing Mode

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  1. Instruction Classification and Addressing Mode 计算机学院 李征 Tel：13882153765 Email：lizheng@cs.scu.edu.cn OICQ: 1340915

  2. Assembler and Machine Instruction • In principle, assembler instruction correspond with machine instruction one by one. • However, there are few exceptions. • Because it is easy to remember, programmer only learn assembler instructions.

  3. Assembler and Machine Instruction • The syntax restriction in assembler instructions are introduced from corresponding machine instructions. • These syntax restrictions is decided by CPU architecture.

  4. Instruction Composition • OPR DEST, SRC • OPR: Operation Code to present instruction function • SRC: Source data for operation • DEST: Destination address for operation result, maybe provide source data too

  5. Instruction Classification (1) • 1) Instruction with two operation data • OPR DEST, SRC • DEST can be register, memory cell • SRC can be register, memory cell, immediate data (立即数)

  6. 1) Instruction with two operation data • DEST and SRC can be 8-bit or 16-bit. • The length of DEST and SRC must be consistent. • Only one memory cell can appear at DEST or SRC.

  7. 1) Instruction with two operation data • Example: • MOV AX, BX ;1 SRC, 1 DEST • MOV VAR1, BL • MOV AL, 08H • ADD AL, BL ;2 SRC, 1 DEST • Error Usage: • MOV 32H, AL • MOV AL, 9A4BH • MOV VAR1, VAR2

  8. Instruction Classification (1) • 2) Instruction with one operation data • OPR DEST • Actually, one or two data are both possible. • DEST can be register or memory cell, 8-bit or 16-bit • Note: Immediate data can not used in instructions with one data.

  9. 2) Instruction with one operation data • Examples: • NEG AX ; 1 SRC, 1 DEST • PUSH AX ; 1 SRC, 1 implied DEST • Error Usage: • PUSH 2A45H

  10. Instruction Classification (1) • 3) Instruction with no operation data • OPR • Actually, one or two data are possible too.

  11. 3) Instruction with no operation data • Example: • NOP ; No SRC and DEST • CLC ; 1 implied DEST • POPF ; 1 implied SRC, 1 implied DEST

  12. Instruction Classification (2) • 1) Transfer instruction • 2) Arithmetic instruction • 3) Bit Manipulation instruction • 4) String instruction • 5) Program transfer instruction • 6) Processor control instruction

  13. Addressing Mode • Addressing mode means how CPU obtain the operation data in instructions. • (1) Register Addressing • (2) Immediate Addressing • (3) Memory Addressing • (4) String Addressing • (5) I/O Port Addressing

  14. Addressing Mode • Addressing Mode is a concept for operation data, not for instruction. • If there are two operation data in an instruction, there may be two different addressing modes. • Example: MOV AX, VAR1 • DEST: Register Addressing • SRC: Memory Addressing

  15. (1) Register Addressing • If operation data is in CPU register, the addressing mode is register addressing. • Example: • mov al, bl • DEST: Register addressing • SRC: Register addressing

  16. (1) Register Addressing • Because no bus operation needed in register addressing, it is the fastest addressing mode of CPU.

  17. (2) Immediate Addressing • If the operation data is immediate data in instructions, the addressing mode is immediate addressing. • Example: • mov al, 02h • DEST: Register Addressing • SRC: Immediate Addressing

  18. (2) Immediate Addressing • Because immediate data is part of instruction, it will be loaded to instruction queue in instruction reading cycle (not execution cycle). • Bus operation is needed for reading data. • However, because EU and BIU can work synchronously, the time consumed in immediate data reading can be ignored in some situations.

  19. Memory Addressing • When operation data is in memory, the addressing mode is memory addressing. • Bus operation is needed in this addressing mode, and memory Addressing must be executed in execution cycle of instruction. • Then, memory addressing is less effective than register or immediate addressing.

  20. Memory Addressing • Memory logic address is composed of segment base value and offset (effective address). • There are five different memory addressing modes, and they have different offset (EA) composing.

  21. Components of EA • There are three different components which can be combined to EA. • DISP (Disparity, 位移量): EA components provided by machine instruction • Base Component (基址分量): Provided by BX or BP register • Index Component (变址分量): Provided by SI or DI register

  22. Memory Addressing • Different combination mode of these three components forms different memory addressing. • 1) Direct Addressing (直接寻址) • 2) Register Indirect Addressing (寄存器间接寻址) • 3) Based Addressing (基址寻址) • 4) Indexed Addressing (变址寻址) • 5) Based Indexed Addressing (基址变址寻址)

  23. 1) Direct Addressing • If EA is composed of DISP only, it is direct addressing. • EA = DISP • DISP may be data form or symbol form in assembler language.

  24. 1) Direct Addressing • Example: • MOV BX, [1000H] • ; implied DS for segment information • MOV BX, DS:[1000H] • MOV BX, ES:[0100H]

  25. 1) Direct Addressing • Example: • MOV BX, VAR1 • ; VAR1 is a symbol disparity. • MOV AL, DA1+3 • ; DA1 is a symbol disparity. • Symbol disparity will be replaced as data form by assembler (汇编程序).

  26. 1) Direct Addressing • False usage: • MOV [0100H], 04H • ; 16-bit or 8-bit? It is a syntax error. • Correct one: • MOV BYTE PTR [0100H], 04H

  27. 2) Register Indirect Addressing • If EA is provided by one register entirely, it is register indirect addressing. • EA = （BX） • EA = （BP） • EA = （SI） • EA = （DI）

  28. 2) Register Indirect Addressing • Examples: • MOV AL, [BX] • MOV BYTE PTR [SI], 03H • ADD [DI], BL • ; BX, SI, and DI imply DS • MOV [BP], AX ;BP imply SS • ADD DS:[BP], AL

  29. 3) Based Addressing • If EA is composed of base component and DISP, it is based addressing. • EA = （BX）+ Disp • EA = （BP）+ Disp

  30. 4) Indexed Addressing • If EA is composed of index component and DISP, it is indexed addressing. • EA = （SI）+ Disp • EA = （DI）+ Disp

  31. Based Addressing and Indexed Addressing • Example: • MOV AX， 10H[SI] • DEST: Register Addressing • SRC: Indexed Addressing, EA = 10H+(SI), DS is implied.

  32. Based Addressing and Indexed Addressing • Example: • MOV TAB1[BP]， CL • DEST: Based addressing, EA=TAB1+(BP), and SS is implied. • SRC: Register addressing

  33. Based Addressing and Indexed Addressing • Do you remember the 1D array in high-level language? • BX, BP, SI, DI can be the subscript variable when the array is operated.

  34. 5) Based Indexed Addressing • If EA is composed of three components, it is based indexed addressing. • EA = （BX）+（SI）+ Disp • EA = （BX）+（DI）+ Disp • EA = （BP）+（SI）+ Disp • EA = （BP）+（DI）+ Disp • BX imply DS, and BP imply SS.

  35. 5) Based Indexed Addressing • Example: • MOV AX， 200H[BX][SI] • SRC: Based indexed addressing, EA = 200H+(BX)+(SI), DS is implied.

  36. 5) Based Indexed Addressing • Example: • MOV TAB1[BP][DI]， DL • DEST: Based indexed addressing, EA = TAB1+(BP)+(DI), and SS is implied. • Do you remember 2D arrays in high-level language? • How about n-D arrays?

  37. Note in Memory Addressing • ; Are they different? • MOV AL，[BX] ; not use ALU • MOV AL，10H[BX] ; ALU used • ; Are they different? • MOV AL，[BX][SI] • MOV AL，20H[BX][SI]

  38. (4) String Addressing • In string operation instructions, the addressing mode are all string addressing. • No time for string operation now, sorry!

  39. (5) I/O port Addressing • When operation data is in I/O port, the addressing mode is I/O port addressing. • In 8086/8088, the I/O operation and memory operation are distinguished by control signal on system bus. • So, different instructions used to I/O and memory operation.

  40. (5) I/O port Addressing • In 8086/8088, only input and output instruction can operate I/O port. • All instructions which can operate memory cell can not operate I/O port.

  41. (5) I/O port Addressing • Unlike the 20-bit physic address of memory cell, the physic address of I/O port is only 16-bit. • When I/O operation occurs, only lower 16 bits of address bus is valid. • There is no segment management in I/O port space.

  42. (5) I/O port Addressing • There are two addressing modes for I/O port addressing. • Direct Addressing: Port address is provided by instruction. • Indirect Addressing: Port address is provided by DX register.

  43. (5) I/O port Addressing • Example: • IN AL, 60H ; 8-bit operation • SRC: Direct I/O port addressing, can only provide address as 0~255 (8 bit address) • OUT 40H, AX ;16-bit operation

  44. (5) I/O port Addressing • Example: • MOV DX, 0FF55H • IN AL, DX • SRC: Indirect I/O port addressing, can provide 16-bit port address (0~65535) • 64K is the I/O space size in 8086/8088.

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