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Clocking & Timing

Clocking & Timing. EE116B (Winter 2000): Lecture # 18 March 9, 1999. The Clock Skew Problem. Delay of Clock Wire. Constraints on Skew. Clock Constraints in Edge Triggered Logic. Positive and Negative Skew. Clock Skew in Master-Slave 2-Phase Design. Clock Skew in 2-Phase Design.

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Clocking & Timing

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  1. Clocking & Timing EE116B (Winter 2000): Lecture # 18 March 9, 1999

  2. The Clock Skew Problem

  3. Delay of Clock Wire

  4. Constraints on Skew

  5. Clock Constraints in Edge Triggered Logic

  6. Positive and Negative Skew

  7. Clock Skew in Master-Slave2-Phase Design

  8. Clock Skew in 2-Phase Design

  9. How to Counter Clock Skew?

  10. Clock Distribution

  11. Clock Network with Distributed Buffering

  12. Example: DEC Alpha 21164 • Clock frequency: 300MHz • 9.3 Million transistors • Total clock load: 3.75 nF • Power in clock distribution network: 20W • out of 50W • Uses two level clock distribution • single 6-stage buffer at the center of the chip • secondary buffers drive left and right side clock grid in Metal3 and Metal4 • Total driver size: 58 cm !

  13. Clock Skew in Alpha Processor

  14. Self-timed and Asynchronous Design • Functions of clock in synchronous design • acts as completion signal • ensures the correct ordering of events • Truly asynchronous design • completion is ensured by careful timing analysis • ordering of events is implicit in logic • Self-timed design • completion ensured by a completion signal • ordering imposed by handshaking protocol

  15. Self-timed Pipelined Datapath

  16. Completion Signal Generation

  17. Completion Signal Generation Using Redundant Signal Encoding

  18. Completion Signal UsingDCVSL Logic

  19. Self-timed Adder

  20. Hand-shaking Protocol

  21. Event Logic: the Muller C-Element

  22. 2-phase Handshake Protocol

  23. Example: Self-timed FIFO

  24. 4-phase Handshake Protocol(or, RTZ)

  25. 4-phase Handshake Protocol (Implementation)

  26. Asynchronous-Synchronous Interface

  27. A Simple Synchronizer

  28. Synchronizer: Output Trajectories

  29. Simulated Trajectory vs. One Pole Model

  30. Mean Time to Failure

  31. Example

  32. Cascaded Synchronizers Reduce MTF

  33. Arbiters

  34. Synchronization at System Level

  35. Skew of Local Clocks vs. Reference

  36. Phase-Locked Loop Based Clock Generator

  37. Ring Oscillator

  38. Example of PLL-generated Clock

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