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Serial Communication Interface

Serial Communication Interface. Mohamad KAHLIL. Serial Communication. Transmit bits in a single channel simplex (one way) half-duplex (one direction at a time) full-duplex (two way) A sequence of bits – packet or character

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Serial Communication Interface

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  1. Serial Communication Interface Mohamad KAHLIL

  2. Serial Communication • Transmit bits in a single channel • simplex (one way) • half-duplex (one direction at a time) • full-duplex (two way) • A sequence of bits – packet or character • ASCII code – 7 bits for 128 characters (alphabet, numerical, and control) • fixed length or variable length • Start, stop, and parity bits

  3. Synchronous communication • A common synchronous transmission method associates a clock pulse with each bit transmitted. This requires two communications media, one for the data bits and one for the clock pulses. The receiver easily recognizes the data bits because they occur with the clock pulses

  4. EIA RS232 • Connection and signal characteristics • Data terminal equipment and data communication equipment • Logic '1' (marking) – -3v to -25v with respect to signal ground • Logic “0” (spacing) – +3v to +25v • Not assigned –between -3v and +3v (a transition region)

  5. DTE FEP DB25 DCE MOD DB25 1 FG --------------- 1 FG 2 TX --------------> 2 TX 3 RX <-------------- 3 RX 4 RTS --------------> 4 RTS 5 CTS <-------------- 5 CTS 6 DSR <-------------- 6 DSR 7 SG --------------- 7 SG 8 DCD <-------------- 8 DCD 20 DTR --------------> 20 DTR RS232 (continued) • Flow control (handshaking) signals to avoid buffer overflow or lock-up. • RTS – to prepare the DCE device for accepting transmitted • CTS -- to inform the DTE device that transmission may begin • DCD: data carrier detected • DSR: DCE ready • SG: system ground • DTR: DTE ready

  6. Signal Format for ASCII CharacterAsynchronous communication • data, start, stop, and (even or odd) parity bits

  7. Basic Operations • We needs: • Parallel / serial conversion • Buffering • Clock synchronization and Data sampling • Solution: Serial interface like 6850

  8. MC6850 • Asynchronous communication interface adapter (ACIA) • Universal Asynchronous Receiver/Transmitter (UART) 8250, 16540, etc. • Pins: • D0-D7 – bi-directional data • CS0, CS1, and CS2 for chip select • E clock, R/W, IRQ • RS for register select (0 for status/control, 1 for data) • Rx and Tx clock • Rx and Tx data • CTS (clear to send), DCD (data carrier detect), RTS (request to send)

  9. MC6805 Architecture

  10. ACIA registers • Status register • Read the status of transmission and reception, errors • Control register • To program the speed and the data format • Data receive register • Used to send data • Data transmit register • Used to receive data

  11. How to operate MC6850 • Hardware and signals – • chip selection from address decoder • data bus • Rx and Tx clocks • Software — • read from status register to know the ACIA status • write to control register to change ACIA configuration • if receive data register if full (RDRF in status register), read from receive data register • if transmit data register is empty (TDRE in status regsiter), write to transmit data register

  12. Programming of MC6850 • ACIA is addressable at two memory locations • For example: $FFE0 and $FFE1 (A0 is connected to RS) • Control register (write only) • CR 0-1: counter divider (00 for 1, 01 for 16, 10 for 64) and master reset (11) • CR 2-4: data format (# of data bits, stop bits, parity) • CR 5-6: TX interrupt (if TDRE) and RTS (low or high) • CR 7: Rx interrupt (if RDRF)

  13. Programming the data format

  14. Programming of 6850 (continued) • Status register (read only) • bit 0: RDRF -- 0 after CPU read or reset and 1 after data received • bit 1: TDRE – 1 if done, 0 if full • bit 2: DCD – high if DCD is high (carrier is not presented) • bit 3: CTS – low if CTS • bits 4, 5, 6 – framing error, receiver overrun, and parity error • bit 7: interrupt – high if interrupt occurs (IRQ), cleared after read to RDR or write to TDR

  15. Programming of 6850 (continued) • Reset – write to CR 0-1 • set RTS and IRQ (CR 5-6) • set format and clock divider (CR 0-4) • Receive – • wait until RDRF=1 read in data from RDR • initiate an interrupt service routine • if interrupt when RDRF=1 • CPU interrupted, read RDR • Transmit – • wait until TDRE=1 write data to TDR

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