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NetFPGA Programmable Networking for High-Speed Network Prototypes, Research and Teaching

NetFPGA Programmable Networking for High-Speed Network Prototypes, Research and Teaching. Berlin – November 10th, 2011. Presented by: Andrew W. Moore (University of Cambridge) CHANGE/OFELIA Berlin, Germany November 10th, 2011 http://NetFPGA.org. Tutorial Outline.

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NetFPGA Programmable Networking for High-Speed Network Prototypes, Research and Teaching

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  1. NetFPGA Programmable Networking for High-Speed Network Prototypes, Research and Teaching Berlin – November 10th, 2011 Presented by: Andrew W. Moore (University of Cambridge) CHANGE/OFELIA Berlin, Germany November 10th, 2011 http://NetFPGA.org

  2. Tutorial Outline Berlin – November 10th, 2011 • Motivation • Introduction • The NetFPGA Platform • Hardware Overview • NetFPGA 1G • NetFPGA 10G • The Stanford Base Reference Router • Motivation: Basic IP review • Example 1: Reference Router running on the NetFPGA • Example 2: Understanding buffer size requirements using NetFPGA • Community Contributions • Altera-DE4 NetFPGA Reference Router (UMassAmherst) • NetThreads (University of Toronto) • Concluding Remarks

  3. Berlin – November 10th, 2011 Section I: Motivation

  4. NetFPGA = Networked FPGA Berlin – November 10th, 2011 A line-rate, flexible, open networking platform for teaching and research

  5. NetFPGA consists of… Berlin – November 10th, 2011 NetFPGA 1G Board NetFPGA 10G Board Four elements: • NetFPGA board • Tools + reference designs • Contributed projects • Community

  6. NetFPGA Board Comparison Berlin – November 10th, 2011

  7. NetFPGA board Berlin – November 10th, 2011 1GE 1GE 1GE 1GE Memory Memory CPU FPGA NetFPGA Board PC with NetFPGA NetworkingSoftware running on a standard PC PCI A hardware accelerator built with Field Programmable Gate Arraydriving Gigabit network links

  8. Tools + Reference Designs Berlin – November 10th, 2011 Tools: • Compile designs • Verify designs • Interact with hardware Reference designs: • Router (HW) • Switch (HW) • Network Interface Card (HW) • Router Kit (SW) • SCONE (SW)

  9. Contributed Projects Berlin – November 10th, 2011 More projects: http://netfpga.org/foswiki/NetFPGA/OneGig/ProjectTable

  10. Community Berlin – November 10th, 2011 Wiki • Documentation • User’s Guide • Developer’s Guide • Encourage users to contribute Forums • Support by users for users • Active community - 10s-100s of posts/week

  11. International Community Berlin – November 10th, 2011 Over 1,000 users, using 1,900 cards at 150 universities in 32 countries

  12. NetFPGA’s Defining Characteristics Berlin – November 10th, 2011 • Line-Rate • Processes back-to-back packets • Without dropping packets • At full rate of Gigabit Ethernet Links • Operating on packet headers • For switching, routing, and firewall rules • And packet payloads • For content processing and intrusion prevention • Open-source Hardware • Similar to open-source software • Full source code available • BSD-Style License • But harder, because • Hardware modules must meeting timing • Verilog & VHDL Components have more complex interfaces • Hardware designers need high confidence in specification of modules

  13. Test-Driven Design Berlin – November 10th, 2011 • Regression tests • Have repeatable results • Define the supported features • Provide clear expectation on functionality • Example: Internet Router • Drops packets with bad IP checksum • Performs Longest Prefix Matching on destination address • Forwards IPv4 packets of length 64-1500 bytes • Generates ICMP message for packets with TTL <= 1 • Defines how packets with IP options or non IPv4 … and dozens more … Every feature is defined by a regression test

  14. Who, How, Why Berlin – November 10th, 2011 Who uses the NetFPGA? • Teachers • Students • Researchers How do they use the NetFPGA? • To run the Router Kit • To build modular reference designs • IPv4 router • 4-port NIC • Ethernet switch, … Why do they use the NetFPGA? • To measure performance of Internet systems • To prototype new networking systems

  15. Berlin – November 10th, 2011 Section II: Hardware Overview

  16. NetFPGA-1G Berlin – November 10th, 2011

  17. Xilinx Virtex II Pro 50 Berlin – November 10th, 2011 • 53,000 Logic Cells • Block RAMs • Embedded PowerPC

  18. Network and Memory Berlin – November 10th, 2011 • Gigabit Ethernet • 4 RJ45 Ports • Broadcom PHY • Memories • 4.5MB Static RAM • 64MB DDR2 Dynamic RAM

  19. Other IO Berlin – November 10th, 2011 • PCI • Memory Mapped Registers • DMA Packet Transferring • SATA • Board to Board communication

  20. NetFPGA-10G Berlin – November 10th, 2011 • A major upgrade • State-of-the-art technology

  21. Comparison Berlin – November 10th, 2011

  22. 10 Gigabit Ethernet Berlin – November 10th, 2011 • 4 SFP+ Cages • AEL2005 PHY • 10G Support • Direct Attach Copper • 10GBASE-R Optical Fiber • 1G Support • 1000BASE-T Copper • 1000BASE-X Optical Fiber

  23. Others Berlin – November 10th, 2011 • QDRII-SRAM • 27MB • Storing routing tables, counters and statistics • RLDRAM-II • 288MB • Packet Buffering • PCI Express x8 • PC Interface • Expansion Slot

  24. Xilinx Virtex 5 TX240T Berlin – November 10th, 2011 • Optimized for ultra high-bandwidth applications • 48 GTX Transceivers • 4 hard Tri-mode Ethernet MACs • 1 hard PCI Express Endpoint

  25. Beyond Hardware Berlin – November 10th, 2011 MicroBlaze SW PC SW Reference Designs Wiki, GitHub, User Community AXI4 IPs Xilinx EDK • NetFPGA-10G Board • Xilinx EDK based IDE • Reference designs with ARM AXI4 • Software (embedded and PC) • Public Repository (GitHub) • Public Wiki (PBWorks)

  26. NetFPGA-1G Cube Systems Berlin – November 10th, 2011 • PCs assembled from parts • Stanford University • Cambridge University • Pre-built systems available • Accent Technology Inc. • Details are in the Guide http://netfpga.org/static/guide.html

  27. Rackmount NetFPGA-1G Servers Berlin – November 10th, 2011 NetFPGA inserts in PCI or PCI-X slot 2U Server (Dell 2950) 1U Server (Accent Technology Inc.) Thanks: Brian Cashman for providing machine

  28. Stanford NetFPGA-1G Cluster Berlin – November 10th, 2011 • Statistics • Rack of 40 • 1U PCs with NetFPGAs • Managed • Power • Console • LANs • Provides 4*40=160 Gbps of full line-rate processing bandwidth

  29. Berlin – November 10th, 2011 Section III: Network review

  30. Internet Protocol (IP) Berlin – November 10th, 2011 IP Hdr IP Hdr IP Hdr IP Hdr Eth Hdr Eth Hdr Eth Hdr IP Hdr IP Hdr Data Data Data Data Data Data Data Data to be transmitted: … IP packets: … Ethernet Frames:

  31. Destination Address Flags Fragment Offset Internet Protocol (IP) HLen T.Service Total Packet Length 16 32 Fragment ID 1 Options (if any) Ver Source Address Header Checksum Protocol TTL 4 20 bytes Berlin – November 10th, 2011 IP Hdr Data Data …

  32. Basic operation of an IP router R3 R1 Berlin – November 10th, 2011 D R4 D A Destination Next Hop D R3 E R3 B E F R5 R2 C R5 F

  33. Basic operation of an IP router R3 Berlin – November 10th, 2011 R1 R4 D A B E R2 C R5 F

  34. Forwarding tables Berlin – November 10th, 2011 IP address 32 bits wide → ~ 4 billion unique address Naïve approach: One entry per address ~ 4 billion entries Improved approach: Group entries to reduce table size

  35. IP addresses as a line Berkeley Stanford Your computer My computer Berlin – November 10th, 2011 North America Asia All IP addresses 0 232-1

  36. Longest Prefix Match (LPM) Most specific Berlin – November 10th, 2011 To: Stanford Data • Matching entries: • Stanford • North America • Everywhere Universities Continents Planet

  37. Longest Prefix Match (LPM) Most specific Berlin – November 10th, 2011 To: Canada Data • Matching entries: • North America • Everywhere Universities Continents Planet

  38. Implementing Longest Prefix Match Berlin – November 10th, 2011 Searching FOUND Most specific Least specific

  39. Basic components of an IP router Management & CLI Routing Protocols Routing Table Berlin – November 10th, 2011 Forwarding Table Switching Queuing Software Control Plane Data Plane per-packet processing Hardware

  40. IP router components in NetFPGA Input Arbiter Management & CLI Management & CLI Output Port Lookup Routing Protocols Routing Protocols Routing Table Routing Table Output Queues SCONE Linux Berlin – November 10th, 2011 Router Kit Forwarding Table Queuing Switching OR Software Hardware

  41. Berlin – November 10th, 2011 Section IV: Example I

  42. Operational IPv4 router SCONE Java GUI Reference router Management & CLI Routing Protocols Routing Table Berlin – November 10th, 2011 Forwarding Table Switching Queuing Control Plane Software Data Plane per-packet processing Hardware

  43. Streaming video Berlin – November 10th, 2011

  44. Streaming video Berlin – November 10th, 2011 NetFPGA running reference router PC & NetFPGA (NetFPGA in PC)

  45. Streaming video Berlin – November 10th, 2011 Video streaming over shortest path Video client Video server

  46. Streaming video Berlin – November 10th, 2011 Video client Video server

  47. Observing the routing tables Berlin – November 10th, 2011 • Columns: • Subnet address • Subnet mask • Next hop IP • Output ports

  48. Example 1 Berlin – November 10th, 2011 http://www.youtube.com/watch?v=xU5DM5Hzqes

  49. Review Exercise 1 Berlin – November 10th, 2011 NetFPGA as IPv4 router: • Reference hardware + SCONE software • Routing protocol discovers topology Example 1: • Ring topology • Traffic flows over shortest path • Broken link: automatically route around failure

  50. Berlin – November 10th, 2011 Section IV: Example II

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