1 / 21

A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio

Compound Semiconductor IC Symposium. A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio. Mehdi Khanpour +, Sorin Voinigescu +, M. T. Yang* + University of Toronto, *TSMC October 2007. Outline. Motivation 60-GHz Radio PA schematic Fabrication Measurement results Conclusion.

dasan
Télécharger la présentation

A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Compound Semiconductor IC Symposium A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio Mehdi Khanpour+, Sorin Voinigescu+, M. T. Yang* +University of Toronto, *TSMC October 2007

  2. Outline • Motivation • 60-GHz Radio • PA schematic • Fabrication • Measurement results • Conclusion Mehdi Khanpour

  3. Motivation • 60-GHz Band (57-64 GHz) • Large bandwidth and limited propagation • High data rate (4+Gbps), short range • Personal Area Networks, Wireless HDTV • CMOS alternative • lower power • higher integration and lower cost Mehdi Khanpour

  4. 60-GHz Radio • Simple narrow-band radio architecture • Implemented in 90nm CMOS • Receiver w/o VCO [1] • Up-converter [2] • Power Amplifier (this work) Mehdi Khanpour

  5. PA Schematic • Input designed as LNA with inductive feedback • Input matched by LG and LS • Output designed as PA with source degeneration for linearity Mehdi Khanpour

  6. PA Design • Stage 1 biased at 0.2 mA/μm and sized for simultaneous noise and input impedance matching • Stage 2 and 3 biased at 0.3 mA/μm for linearity • Output stage sized for PSAT = 6.5 dBm with Inductive degeneration for linearity • Inductors and interconnects modeled using ASITIC Mehdi Khanpour

  7. Fabrication • Fabricated in TSMC 90nm GP CMOS • 9-layer Cu back-end, no “thick” metal Large signal test setup: 67GHz Cable 110GHz Cable 67GHz Infinity Probes 50GHz Bias T 300μm× 500μm Mehdi Khanpour

  8. Simulations • 18 dB Gain, 4.5 dB NF • Γopt, S11 and S22 < -10 dB from 50-68 GHz Mehdi Khanpour

  9. Measurement vs. Simulation • 14 dB Gain, 3dB bandwidth extends from 48-61 GHz • S11 and S22 < -10 dB from 48-65 GHz Mehdi Khanpour

  10. Measurement vs. Simulation • Measurement shows 14 dB gain @ 55 GHz • Diffusion region in layout is wider than the minimum allowed by design kit • Extra capacitance pushing the centre frequency down is not captured in simulations Mehdi Khanpour

  11. Measurement vs. Simulation • S21 peaks at 55 GHz when extra capacitance is added Mehdi Khanpour

  12. S-Parameters Across 5 Dies • Results show excellent repeatability Mehdi Khanpour

  13. S21 vs. Power Supply • 2 dB drop in gain from 1.5V to 1.2V supply Mehdi Khanpour

  14. Linearity Measurement • 6 dBm PSAT, 1.6 dBm P1dB • Maximum PAE is 6% @ 55 GHz and 5.2% @ 60 GHz, η = 22% Mehdi Khanpour

  15. Linearity vs. Current Density • Optimal linearity bias coincides with peak fT current density of 0.3~0.35 mA/μm Mehdi Khanpour

  16. Temperature Measurements • Gain decreases by 5 dB and PSAT by 2dBm from 25oC to 100oC Mehdi Khanpour

  17. Scaling • Same concept implemented in 65nm at 80 GHz • Third stage is cascode with identical size (40 μm) • Higher gain but lower PSAT due to cascode output stage, η = 11% Mehdi Khanpour

  18. PA Comparison Mehdi Khanpour

  19. Conclusion • 60-GHz PA with 14 dB gain demonstrated in 90nm CMOS • PA characterized over process, supply voltage and temperature variation • Results show excellent yield and repeatability • Scalable to 80 GHz in 65nm CMOS Mehdi Khanpour

  20. Acknowledgment • Jaro Pristupa and CMC for CAD tools and support • OIT and CFI for equipment grants • TSMC for facilitating the technology access Mehdi Khanpour

  21. References [1] D. Alldred et al, CSICS 2006 [2] S. P. Voinigescu et al, ISCAS 2007 [3] T. Yao et al. RFIC-Symp 2006 [4] B. Floyd et al, ISSCC 2004 [5] S. T. Nicolson et al, IMS 2007 Mehdi Khanpour

More Related