L11 110816 ECE 4243/6243 Fall 2016 UConn F. Jain

1. L11 110816 ECE 4243/6243 Fall 2016 UConn F. Jain Notes Chapter L11 (page 226-166). FET Operation slides 3-8 3-Scaling Laws of FETs (slides 9-22)

2. VT or VTH equation Al-SiO2-pSi Al-SiO2-nSi

3. Under Threshold MOS charge density distribution and Energy bands Al-SiO2-pSi Under Inversion

4. Equilibrium & Flat Band MOS charge density distribution and Energy bandsAl-SiO2-pSi Accumulation If VG =0, there is some band bending. The bending is determined by the work funciton difference between metal and p-Si and oxide charge Qox. The band bending is equal to VFB. Some of it drops across the depletion layer and rest across the oxide. If VG is made negative and equal to VFB, the band becomes flat. The charge density is zero all over. If VG is made negative and greater than VFB, the band bends upward in pSi. The charge density is in the accumulation layer.

5. MOS FET Equationsn-channel Al-SiO2-pSi N-inversion channel FET. Enhancement FET. • Two type of n-channel FETs. • Enhancement type where a channel is induced on the surface of p-Si once the gate voltage is above threshold. • Depletion type, here, there is a built-in n-layer of Si serving as n-channel on p-Si is depleted.

6. Saturation region Case II Saturation region Case I

7. ID-Vg, ID-VdSee page 545 and 546 for summary Id Vd

8. 3-Scaling Laws of FETs Constant electric field (CE) Constant voltage (CV) and quasi constant voltage (QCV) Generalized scaling (GS) Paper by Baccharani et al, 1984 Nanotransistor issues (page 230) Degradation mechanisms (p.241-248) Nanofet Design

9. Scaling Laws (p.2330 Constant electric field (CE): The central point is to maintain electric field constant in the gate oxide and in the depletion region, after scaling down the dimensions. Thus, L, W, tox, are reduced by a factor k, voltages are reduced by the same factor k, and substrate doping is increased by k. 1. Linear dimensions are reduced by a factor k: L, W, TOX are divided by k (k>l) to obtain scaled-down values. e.g. L' = L/k, W' = W/k, T'OX = TOX/k (1) 2. Voltages are reduced by k. e.g. V'DS = VDS/k, V'GS = VGS/k (2) 3. Substrate doping is increased by k. e.g. N'A = NA* k (3) The applied voltages are reduced to maintain electric field strengths as in the case of long-channel or un-scaled devices. In case of substrate doping, the rationale is to keep the depletion width x'p = xp/k

10. Scaling Laws the scaled-down potentials/voltages ϕ' = ϕ/k here, k >1 the scaled-down dimensions (x',y',z') = (x,y,z)/λ here, λ >1 the scaled-down concentrations (n',p',N'D,N'A) = (n,p,ND,NA)/δ It will be shown, following Baccarani et al that δ = k/λ2, if potential distribution shapes are to be preserved in scaled- down devices. Generalized scaling (GS)

11. Scaling Laws CV + QCV are summarized below in Table II TABLE II Note: k>1 k>β>1

12. Scaling

13. Design steps using GS 1. Find dimensional scaling l from existing channel dimensions and desired scaled- down 2. Using processing parameters, determine threshold variation DVTH Determine VTH (=~4 DVTH) and VDD (VDD ~4*VTH) 3. Find the scaling for voltages k 4. Compute the scaling factor d for doping.

14. DVTH Dopant density variation (due to implant or in substrrate) Oxide or gate insulator thickness variation Oxide dielectric constant variation in thin films of 1-2nm Channel width and length variation, Oxide charge density variation

15. Verification of scaled-down design 1. Is the oxide thickness realistic in terms of gate leakage current? 2. Is supply voltage and threshold realistic in terms of source to drain tunneling? 3. Is the device to device fluctuation in a die and in dies in a wafer acceptable? 4. Is the drive current acceptable? Is the ID-VG and ID-VD characteristics ok in terms of fan-in and fan-out and logic noise margins?

16. Direct Tunneling Ef As FET dimensions are reduced, tunneling can occur • Scaling of parameter relationships • Operation as partially depleted or fully depleted Nano-transistor scaling issues p. 230 • 3. Channel to gate tunneling for thin oxides: • Fowler-Nordheim tunneling; • b. Direct Tunneling • 4. Source to drain tunneling, gate loses control 5. Trapping of channel electron under gate oxide Barrier Hopping Fowler-Nordheim Tunneling

17. Degradation Mechanisms (242) 1.Poly-Si gate depletion and increased gate capacitance Poly silicon region: Poly-Si may be implanted during processing using ion implantation. However, with this method, some poly-Si atoms will penetrate through the oxide, causing problems. This damage the gate insulator. The charge in poly-silicon gate depletion represents capacitance.

18. Degradation Mechanisms (242) 2. Source to drain tunneling.

19. Degradation Mechanisms (242) 3. Channel to gate tunneling.

20. Degradation Mechanisms (242) 4. GIDL.

21. Degradation Mechanisms (242) 5. Oxide Breakdown • Oxide (dielectric) breakdown As we have seen, significant electron tunneling can occur when a large electric field is applied across an oxide layer. This tunneling can lead to a condition called dielectric breakdown, after which an oxide layer ceases to be a good electrical insulator. Dielectric breakdown can occur either softly (i.e. gradually) or abruptly. The physical mechanisms involved in, and leading to, dielectric breakdown involve: • impact ionization in the oxide layer • injection of holes • creation of electron-hole traps in the oxide • creation of sates at oxide-Si interface

22. Typical plot of charge to breakdown vs. oxide voltage for several oxide thickness values. (Ref: Taur & Ning) Degradation Mechanisms (242) 5. Oxide Breakdown