THE TI OMAP PLATFORM APPROACH TO SOC

1. THE TI OMAP PLATFORM APPROACH TO SOC

2. 5.1 Overview of OMAP5910 5.2 OMAP5910 Block Diagram 5.3 Features 5.4 DSP Subsystem 5.5 Component of DSP Subsystem 5.6 DSP Module Block Diagram 5.7 TMS320C55x DSP Core 5.8 Feature of TMS320C55x 5.9 C55x Block Diagram 5.10 IU 5.11 PU 5.12AU 5.13 DU CONTENTS

3. OMAP Platform general purpose computing engines HW accelerators memory, peripherals and interfaces Platform design parameter Performance Power Cost Time to market SoC Platform - systematic reuse INTRODUCTION

4. OMAP Platform general purpose computing engines HW accelerators memory, peripherals and interfaces Platform design parameter Performance Power Cost Time to market SoC Platform - systematic reuse HIERARCHY OF PLATFORMS INTRODUCTION

5. The OMAP HW/SW Platform

6. KEY COMPONENTS OF WORK Application engineering Reference design SW architecture and development Performance evaluation - Estimation of the workload - Architecture exploration - Archtecture tuning - Performance verification - Silicon evaluation The OMAP HW/SW Platform

7. MULTI-PROCESSOR SW ARCHITECTURE

8. MULTI-PROCESSOR SW ARCHITECTURE 2

9. Ideal socket Dataflow Clock cycle Clocks Reset Interrupt and DMA requests Semantics Scalable performance Higher level functions Extensibility and Flexibility Compliance The TI WIRELESS SoC PLATFORM

10. The TI WIRELESS SoC PLATFORM- Platforms

11. Software issues Port of the OS to basic peripherals Integration of additional devices Commonality Reuse between different OSes The TI WIRELESS SoC PLATFORM- Software

12. Robustness against the evolution of Technology processing scaling high performance additional masters increasing area, decreasing size new high bandwidth modules and workloads additional, heterogeneous smart accelerators The TI WIRELESS SoC PLATFORM- Future Proofing

13. Advantage of Platform based design a wide product range allowing reuse of hardware and software development A hardware architecture adapted to problem A software architecture delivering all the benefits of the hardware to the application developer An efficient SoC platform comprising hardware and low level software A complete and flexible socket allowing hardware to be easily developed, verified and integrated SoC platform definition for hardware and software reuse The TI WIRELESS SoC PLATFORM

14. Highly integrated hardware Software platform designed For next generation embedded devices Unique dual-core architecture TI-enhanced ARMTM 925 processor (TI925T) Command and control TMS320C55xTM DSP core Low-power High-performance Application Mobile communications, Video and image processing, Advanced speech applications, Audio processing, Graphics and video acceleration, Generalized web access, Data processing 5.1 Overview of OMAP5910 [6][7]

15. 5.2 OMAP5910 Block Diagram

16. TI925T MPU subsystem DSP subsystem DSP MMU System DMA controller External memory interfaces Internal SRAM memory External memory traffic controller Mailboxes Endianism conversion Elastic buffering JTAG port Clock management Peripherals 5.3 Features (1/4)

17. TI925T MPU Instruction cache :16K bytes Data cache : 8K bytes MMU 17-word write buffer (WB) Increases system performance DSP (TMS320C55x DSP core) Dual-access RAM (DARAM), single-access (SARAM), ROM Instruction cache Hardware accelerators DMA controller DSP MMU Address translation Access permission checks 5.3 Features (2/4)

18. System DMA controller Six ports, nine channels Additional dedicated DMA : LCD controller Transfer : 8-,16-, or 32-bit Simultaneous transfers Low-power design (no clocking when idle) Two external memory interfaces External memory interface slow (EMIFS) External memory interface fast (EMIFF) Clock management One digital phase-locked loop (DPLL) Three clock management units System power management 5.3 Features (3/4)

19. Peripherals For the MPU For the DSP Shared peripherals 5.3 Features (4/4)

20. 5.4 DSPSub-system

21. DSP module DSP core : TMS320C55x (C55x) Hardware accelerators (HWA) DCT/IDCT Motion estimation Half-pixel interpolation Memories DARAM SARAM PDROM External memory interface (EMIF) 6-channel DMA controller MPUI TIPB 5.5 Component of DSP Subsystem

22. DSP peripherals Three general-purpose 32-bit timers One general-purpose UART 16-signal general-purpose input/output (GPIO) Mailbox For Inter-processor Communication (between MPU and DSP) Watchdog timer Level 2 interrupt handler 5.5 Component of DSP Subsystem

23. 5.6 DSP Module Block Diagram

24. Advanced multiple-bus architecture Unified program/data memory architecture Dual 17 x 17-bit multipliers Add/compare/select (CSSU) unit Exponent encoder Two address generators 8M x 16-bit (16M-bytes) memory space Repeat operations 288MIPS/144MHz, 320MIPS/160MHz, 400MIPS/200MHz, 600MIPS/300MHz ARM9 : 220MIPS/200MHz 0.05 mW/MIPS (20mW) ARM9 : 0.8mW/MHz (160mW) 5.7 TMS320C55x DSP Core

25. Conditional execution Seven-stage pipeline Instruction buffer unit (IU) Program flow unit (PU) Address data flow unit (AU) Data computation unit (DU) 5.7 TMS320C55x DSP Core

26. 64 x 8-bit Instruction buffer queue Two 17 x17-bit MAC units One 40-bit ALU Performs high precision arithmetic and logical operations One 40-bit Barrel Shifter One 16-bit ALU Performs simpler arithmetic in parallel to main ALU Four 40-bit accumulators Twelve independent buses: Three data read buses Two data write buses Five data address buses One program read bus One program address bus 5.8 Feature of TMS320C55x

27. 5.9 C55x

28. DSP processors Fast and powerful performance of digital signal processing operation Specialized instruction set : shift, multiplication, addition Piccolo Digital signal processing unit for ARM7 Licensable core v5TE: signal processing instruction set for ARM-E Teak & TeakLite Synthesizable embedded DSP core Process independent soft core OMAP (TI) : software platform with MCU and DSP core TI925T MPU & TMS320C55x DPS core Summary (1/2)

29. Summary