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STT-MRAM Tapeouts: IBM 65nm & IBM 45nm SOI

Progress Update. STT-MRAM Tapeouts: IBM 65nm & IBM 45nm SOI. Richard Dorrance Advisor: Prof. Dejan Marković November 5, 2010. Review of MTJs. MTJ = Magnetic Tunnel Junction Consists of 3 basic layers Principles of operation

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STT-MRAM Tapeouts: IBM 65nm & IBM 45nm SOI

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  1. Progress Update STT-MRAM Tapeouts:IBM 65nm & IBM 45nm SOI Richard DorranceAdvisor: Prof. Dejan Marković November 5, 2010

  2. Review of MTJs • MTJ = Magnetic Tunnel Junction • Consists of 3 basic layers • Principles of operation • Spin Injector/Polarizer: Ferromagneticlayer spin-polarize a current • Spin Detector: Ferromagnetic layerstend to scatter anti-parallel currents • Two resistive states: • RP: Low Resistance • RAP: High Resistance

  3. STT-MRAM and How it Works • STT = Spin-Torque-Transfer • Use current to flip free layerbetween two resistive states

  4. Integrating STT-MRAM with CMOS • MTJ can integrated on top of CMOS • Typically after M3 or M4 MTJ

  5. Sense Amp for High Speed MTJ Read • Designed by Fengbo • Read Speed:~300ps in 65nm~260ps in 45nm • MTJ reference easilygenerated (“self-biased”)

  6. Pulse Generator A similar circuit is used to measure the Read Delay of the Sense Amp

  7. LFSR Pseudo-Random Counter • LFSR = Linear Feedback Shift Register • High speed counter: can be implementedwith only one XOR for certain bit lengths(i.e. 2, 3, 4, … , 18, …) • For N bits, it can count up to 2N-1 • 4 bit example:

  8. Chip Layout (IBM 65nm) • Array Sizes: • 27.5F2, 35F2, 50F2 • Sharing: 35F2 & 50F2 27F2 50F2 35F2 SHARE

  9. Memory Core (IBM 65nm) 450 μm R MTJ Decoder MUX Data SC 320 μm Read/Write Config SC RD PG MUX MTJ R

  10. Chip Layout (IBM 45nm SOI) • Array Sizes: • 17F2, 25F2, 40F2 • Sharing: 25F2 & 40F2 17F2 25F2 40F2

  11. Memory Core (IBM 45nm SOI) 710 μm 4 8 1 1 2 2 7 3 3 310 μm 6 5 2 2 1 1 8 (1) MTJ Array (2) MUXes (3) Read/Write Circuitry (4) Decoder (5) Configuration Scan Chain (6) Pulse Generation/Read Delay Measurements (7) Data Scan Chain (8) Resistor Arrays

  12. Design Comparison * Based on simulation results

  13. References • C.J. Lin, et al., "45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell," Electron Devices Meeting (IEDM), 2009 IEEE International , vol., no., pp.1-4, 7-9 Dec. 2009 • R. Nebashi, et al., "A 90nm 12ns 32Mb 2T1MTJ MRAM," Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International , vol., no., pp.462-463,463a, 8-12 Feb. 2009 • D. Halupka, et al., "Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.256-257, 7-11 Feb. 2010 • K. Tsuchida, et al., "A 64Mb MRAM with clamped-reference and adequate-reference schemes," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.258-259, 7-11 Feb. 2010

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