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EECS 150 - Components and Design Techniques for Digital Systems Lec 08 – Using, Modeling and Implementing FSMs 9-23-0

EECS 150 - Components and Design Techniques for Digital Systems Lec 08 – Using, Modeling and Implementing FSMs 9-23-04. David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150.

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EECS 150 - Components and Design Techniques for Digital Systems Lec 08 – Using, Modeling and Implementing FSMs 9-23-0

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  1. EECS 150 - Components and Design Techniques for Digital Systems Lec 08 – Using, Modeling and Implementing FSMs9-23-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150 EECS150 F04 Culler Lec 8

  2. Often PLAs Review: What’s an FSM? • Next state is function of state and input • Moore Machine: output is a function of the state • Mealy Machine: output is a function of state and input inputA State / output inputB inputA/outputA State inputB/outputB EECS150 F04 Culler Lec 8

  3. ps ns Review: Formal Design Process Logic equations from table: OUT = PS NS = PS xor IN • Circuit Diagram: • XOR gate for ns calculation • DFF to hold present state • no logic needed for output • Review of Design Steps: 1. Circuit functional specification 2. State Transition Diagram 3. Symbolic State Transition Table 4. Encoded State Transition Table 5. Derive Logic Equations 6. Circuit Diagram FFs for state CL for NS and OUT EECS150 F04 Culler Lec 8

  4. 010 111 001 In = 1 In = 0 In = 0 100 110 In = 1 Review: Finite State Machine Representations • States: determined by possible values in sequential storage elements • Transitions: change of state • Clock: controls when state can change by controlling storage elements • Sequential Logic • Sequences through a series of states • Based on sequence of values on input signals • Clock period defines elements of sequence EECS150 F04 Culler Lec 8

  5. Outline • Review • Typical uses of FSMs • Synchronous Seq. Circuits – safe composition • Timing • FSMs in verilog (reinforcing lab lecture) • State reduction and state assignment EECS150 F04 Culler Lec 8

  6. //Parallel to Serial converter module ParToSer(LD, X, out, CLK); input [3:0] X; input LD, CLK; output out; reg out; reg [3:0] Q; assign out = Q[0]; always @ (posedge CLK) begin if (LD) Q <= X; else Q <= {1’b0,Q[3:1]}; end endmodule // ParToSer Recall: Parallel to Serial Converter • One common use of FSMs is in adapters from one subsystem to another. • different data widths • different bit rates • different protocols, … EECS150 F04 Culler Lec 8

  7. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 Example: Byte-bit stream Byte FIFO init / LD bit 0/pop pop controller Shift register LD Serial link bit 7 / LD EECS150 F04 Culler Lec 8

  8. bit 0’ bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 ~rdy ~rdy ~rdy ~rdy ~rdy ~rdy ~rdy rdy rdy rdy rdy rdy rdy rdy Byte-bit stream with Rate Matching • How would you implement this FSM? Byte FIFO init / LD bit 0/pop ~rdy rdy ~rdy pop controller Shift register LD Serial link rdy bit 7 / LD EECS150 F04 Culler Lec 8

  9. Processor Input Control Memory Datapath Output Another example: bus protocols • A bus is: • shared communication link • single set of wires used to connect multiple subsystems • A Bus is also a fundamental tool for composing large, complex systems (more later in the term) • systematic means of abstraction EECS150 F04 Culler Lec 8

  10. Example: Pentium System Organization Processor/Memory Bus PCI Bus I/O Busses EECS150 F04 Culler Lec 8

  11. Arbitration for the bus… • Central arbitration shown here • Used in essentially all processor-memory busses and in high-speed I/O busses Device 1 Device N Device 2 Req Grant Bus Arbiter EECS150 F04 Culler Lec 8

  12. I still want the bus I’m done after this Proc grabs data Mem grabs addr I want the bus nope You got it Simple Synchronous Protocol • Even memory busses are more complex than this • memory (slave) may take time to respond • it need to control data rate BReq BG CMD Address Rd+Addr Data1 Data2 Data EECS150 F04 Culler Lec 8

  13. Processor Side of Protocol - sketch Idle ~BR • Memory waits? • Additional outputs? • Memory side? proc read Request bus BR BG Address BR,RD, addr_enable ~BG Data 1 BR, MDR_enable Data 2 ~BR, MDR_enable EECS150 F04 Culler Lec 8

  14. I still want the bus You got it I want the bus nope Mem grabs addr Proc grabs data I’m done after this Simple Synchronous Protocol (cont) BReq BG CMD Address Rd+Addr Data1 Data2 Data w-addr idle r-data1 req r-data2 req idle EECS150 F04 Culler Lec 8

  15. CombinationalLogic Inputs Outputs State Inputs State Outputs Storage Elements Fundamental Design Principle • Divide circuit into combinational logic and state • Localize feedback loops and make it easy to break cycles • Implementation of storage elements leads to various forms of sequential logic EECS150 F04 Culler Lec 8

  16. Clock Forms of Sequential Logic • Asynchronous sequential logic – “state” changes occur whenever state inputs change (elements may be simple wires or delay elements) • Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) EECS150 F04 Culler Lec 8

  17. All wires, except clock, may be multiple bits wide. Registers (reg) collections of flip-flops clock distributed to all flip-flops typical rate? Combinational Logic Blocks (CL) no internal state (no feedback) output only a function of inputs Particular inputs/outputs are optional Optional Feedback ALL CYCLES GO THROUGH A REG! General Model of Synchronous Circuit EECS150 F04 Culler Lec 8

  18. Composing FSMs into larger designs FSM FSM CL CL EECS150 F04 Culler Lec 8

  19. next state next state state state output output Composing Moore FSMs • Synchronous design methodology preserved Moore Moore CL CL EECS150 F04 Culler Lec 8

  20. Output Next state Output Next state state state Composing Mealy FSMs … • Synchronous design methodology violated!!! • Why do designers used them? • Few states, often more natural in isolation • Safe if latch all the outputs • Looks like a mealy machine, but isn’t really • What happens to the timing? Mealy FSM CL CL EECS150 F04 Culler Lec 8

  21. How long must this be? What determines this? State register propagation delay Output logic propagation delay FSM timing • What determines min FSM cycle time (max clock rate)? State Time (Clock Period) Clock Inputs Outputs State (internal) EECS150 F04 Culler Lec 8

  22. Announcements • Reading 8.4,7.4, 8.1 • We touched on ideas from chapter 11, not in reader. Will be available on line. EECS150 F04 Culler Lec 8

  23. Finite State Machines in Verilog Mealy outputs Moore outputs next state combinational logic inputs combinational logic current state EECS150 F04 Culler Lec 8

  24. zero[0] 0 1 0 one1[0] 0 1 1 two1s [1] Verilog FSM - Reduce 1s example • Change the first 1 to 0 in each string of 1’s • Example Moore machine implementation module Reduce(Out, Clock, Reset, In); output Out; input Clock, Reset, In; reg Out; reg [1:0] CurrentState; // state register reg [1:0] NextState; // State assignment localparam STATE_Zero = 2’h0, STATE_One1 = 2’h1, STATE_Two1s = 2’h2, STATE_X = 2’hX; EECS150 F04 Culler Lec 8

  25. zero[0] 0 1 0 one1[0] 0 1 1 include all signals that are input to state and output equations two1s [1] Compute: output = G(state) next state = F(state, in) Moore Verilog FSM: combinational part always @(In or CurrentState) begin NextState = CurrentState; Out = 1’b0; case (CurrentState) STATE_Zero: begin // last input was a zero if (In) NextState = STATE_One1; end STATE_One1: begin // we've seen one 1 if (In) NextState = STATE_Two1s; else NextState = STATE_Zero; end STATE_Two1s: begin // we've seen at least 2 ones Out = 1; if (~In) NextState = STATE_Zero; end default: begin // in case we reach a bad state Out = 1’bx; NextState = STATE_X; end endcase end EECS150 F04 Culler Lec 8

  26. zero[0] 0 1 0 one1[0] 0 1 1 two1s [1] Moore Verilog FSM: state part // Implement the state register always @ (posedge Clock) begin if (Reset) CurrentState <= STATE_Zero; else CurrentState <= NextState; end endmodule Note: posedge Clock requires NONBLOCKING ASSIGNMENT. Blocking Assignment <-> Combinational Logic Nonblocking Assignment <-> Sequential Logic (Registers) EECS150 F04 Culler Lec 8

  27. 0/0 zero[0] 1/0 0/0 one1[0] 1/1 Output = G(state, input) Mealy Verilog FSM for Reduce-1s example module Reduce(Clock, Reset, In, Out); input Clock, Reset, In; output Out; reg Out; reg CurrentState; // state register reg NextState; localparam STATE_Zero = 1’b0, STATE_One = 1’b1; always @(posedge Clock) begin if (Reset) CurrentState <= STATE_Zero; else CurrentState <= NextState; end always @ (In or CurrentState) begin NextState = CurrentState; Out = 1’b0; case (CurrentState) zero: if (In) NextState = STATE_One; one: begin // we've seen one 1 if (In) NextState = STATE_One; else NextState = STATE_Zero; Out = In; end endcase endendmodule Note: smaller state machine EECS150 F04 Culler Lec 8 7

  28. Restricted FSM Implementation Style • Mealy machine requires two always blocks • Register needs posedge Clock block • Input to output needs combinational block • Moore machine can be done with one always block, but…. • E.g. simple counter • Very bad idea for general FSMs • This will cost you hours of confusion, don’t try it • We will not accept labs with this style for general FSMs • Use two always blocks! • Moore outputs • Share with state register, use suitable state encoding EECS150 F04 Culler Lec 8

  29. zero[0] 0 1 0 one1[0] 0 1 1 two1s [1] Single-always Moore Machine (Not Allowed!) module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg [1:0] state; // state register parameter zero = 0, one1 = 1, two1s = 2; EECS150 F04 Culler Lec 8

  30. Single-always Moore Machine (Not Allowed!) All outputs are registered always @(posedge clk) case (state) zero: begin out <= 0; if (in) state <= one1; else state <= zero; end one1: if (in) begin state <= two1s; out <= 1; end else begin state <= zero; out <= 0; end two1s: if (in) begin state <= two1s; out <= 1; end else begin state <= zero; out <= 0; end default: begin state <= zero; out <= 0; end endcaseendmodule This is confusing: the output does not change until the next clock cycle EECS150 F04 Culler Lec 8

  31. Finite State Machines • Recommended FSM implementation style • Implement combinational logic using one always block • Implement an explicit state register using a second always block Mealy outputs Moore outputs next state combinational logic inputs combinational logic current state EECS150 F04 Culler Lec 8

  32. State Reduction: Motivation: lower cost fewer flip-flops in one-hot implementations possibly fewer flip-flops in encoded implementations more don’t cares in NS logic fewer gates in NS logic Simpler to design with extra states then reduce later. Example: Odd parity checker. Two machines - identical behavior. FSM Optimization EECS150 F04 Culler Lec 8

  33. State Reduction is based on: Two states are equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state. If two states are equivalent, one can be eliminated without effecting the behavior of the FSM. Several algorithms exist: Row matching method. Implication table method. “Row Matching” is based on the state-transition table: If two states have the same output, and both transition to the same next state, or both transition to each other, or both self-loop, then they are equivalent. Combine the equivalent states into a new renamed state. Repeat until no more states are combined. Note: This algorithm is slightly different than the book. State Reduction EECS150 F04 Culler Lec 8

  34. NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1 Row Matching Example State Transition Table EECS150 F04 Culler Lec 8

  35. NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f e f 0 1 NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1 Row Matching Example (cont) Reduced State Transition Diagram EECS150 F04 Culler Lec 8

  36. State Reduction • The “row matching” method is not guaranteed to result in the optimal solution in all cases, because it only looks at pairs of states. • For example: • Another (more complicated) method guarantees the optimal solution: • “Implication table” method: cf. Mano, chapter 9 • What ‘rule of thumb” heuristics? EECS150 F04 Culler Lec 8

  37. State Maps Assignment State q2 q1 q0 S0 0 0 0 S1 0 0 1 S2 0 1 0 S3 0 1 1 S4 1 1 1 Assignment State q2 q1 q0 S0 0 0 0 S1 1 0 1 S2 1 1 1 S3 0 1 0 S4 0 1 1 • “K-maps” are used to help visualize good encodings. • Adjacent states in the STD should be made adjacent in the map. EECS150 F04 Culler Lec 8

  38. State Assignment Alternative heuristics based on input and output behavior as well as transitions: Adjacent assignments to: states that share a common next state (group 1's in next state map) states that share a common ancestor state (group 1's in next state map) states that have common output behavior (group 1's in output map) EECS150 F04 Culler Lec 8

  39. Summary • FSMs are critical tool in your design toolbox • Adapters, Protocols, Datapath Controllers, … • They often interact with other FSMs • Important to design each well and to make them work together well. • Keep your verilog FSMs clean • Separate combinational part from state update • Good state machine design is an iterative process • State encoding • Reduction • Assignment EECS150 F04 Culler Lec 8

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