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Single Event Latch-up Test

Single Event Latch-up Test. Arkadiusz Dawiec. SEL & SEU test setup. able to monito r 5 chips in parallel able to detect Single Events: Latch-up and Upset maximum test frequency – 1kHz ( limited by PC LPT). SEL test – DUT (device under test). Chip characteristic:

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Single Event Latch-up Test

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  1. Single Event Latch-up Test Arkadiusz Dawiec

  2. SEL & SEU test setup • able to monitor 5 chips in parallel • able to detect Single Events: Latch-up and Upset • maximum test frequency – 1kHz (limited by PC LPT) Arkadiusz Dawiec

  3. SEL test – DUT (device under test) Chip characteristic: • 5 channels : 4 shift registers (64 D flip-flops), 1 IO register (IO pads) • 5 independent power supply • 2 versions of chip : 20µm and 14µm epitaxy Arkadiusz Dawiec

  4. SEL test – DUT cont. Differences between registers • STD & 3B – AMS standard cells • 2µ & 5µstretched registers – distance between complementary transistors was increased: Arkadiusz Dawiec

  5. SEL test – place CYClotron of LOuvain la NEuve (CYCLONE) Used beams: Arkadiusz Dawiec

  6. Arkadiusz Dawiec

  7. SEL test – cross section • for 2u stretched cells latch-up hardness is 2 orders of magnitude better • for 5u we didn’t observe any events Arkadiusz Dawiec

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