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The Performance of Polar Codes for Multi-level Flash Memories

The Performance of Polar Codes for Multi-level Flash Memories . Yue Li joint work with Hakim Alhussien , Erich F. Haratsch , and Anxiao (Andrew) Jiang March 10 th , 2014. NAND Flash Memory. …. Blocks. …. …. …. The circuit board of a SSD. …. 4 pages/WL. Multi-Level Cells.

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The Performance of Polar Codes for Multi-level Flash Memories

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  1. The Performance of Polar Codes for Multi-level Flash Memories Yue Li joint work with Hakim Alhussien, Erich F. Haratsch, and Anxiao (Andrew) Jiang March 10th, 2014

  2. NAND Flash Memory … Blocks … … … The circuit board of a SSD … 4 pages/WL

  3. Multi-Level Cells 2 bits/cell • Four different kinds of pages: • Lower even • Lower odd • Upper even • Upper odd 10 00 01 11

  4. Why Polar Codes? • Desire for optimal ECCs. • Excellent properties • Capacity-achieving • Theoretical guarantee of error floor performance • Efficient encoding and decoding algorithms

  5. Encoding Input User Bits Polar Codeword Flash channels Frozen Channels Frozen bits Noisy Codeword G Information Bits ErdalArıkan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, 2009.

  6. Successive Cancellation Decoding Frozen Channels Estimated user bits Noisy Codeword ErdalArıkan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, 2009.

  7. Successive Cancellation Decoding Frozen Channels Estimated user bits Noisy Codeword ErdalArıkan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, 2009.

  8. Successive Cancellation Decoding Frozen Channels Estimated user bits Noisy Codeword ErdalArıkan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, 2009.

  9. Is polar code suitable for flash memories?

  10. Code Length Adaptation • Polar codes have length N = 2m • The code lengths in flash memory need to be flexible.

  11. Shortening M C Noisy C N – K’ N – K’ K – K’ K’ Est. M K – K’ K’

  12. (N, K, K’)-Shortened Polar Code (x1, x2, …, xN-k’+1, …, xN)=(u1, u2, …, uN-k’+1, …, uN) G (x1, x2, …, 0, …, 0)=(u1, u2, …, 0, …, 0) G ç ç (u1, u2, …, uN-k’+1, …, uN) K’ K’

  13. Evaluation with Random Data Pseudo-random Data (0, 1, 1, 0, …, 1) (1, 0, 1, 0, …, 1) … (1, 0, 1, 0, …, 1) Cycling / Retention (0, 0, 1, 1, …, 1) (1, 0, 0, 0, …, 1) … (0, 0, 1, 1, …, 1) Not generated by polar encoder

  14. Treating Random Data as Codewords (u1, u2, …, uN) = (x1, x2, …, xN) G-1 Invertible Input Channel parameters Output Construct codes Frozen Bits

  15. Hard and Soft Sensing Reference threshold voltages 11 01 00 10 Cell Voltage P( V | bit = 0 ) LLR = log ___________________ P( V | bit = 1 )

  16. Experimental Setup • Construct one polar code for each kind of page. • List successive cancellation decoding [Taland Vardy 2011] • List size = 32with CRC • Block length • 7943 bits shortened from 8192 bits • Code rates • 0.93, 0.94, 0.95 • Flash data • obtained by characterizing 2X-nm MLC flash chips • 6-month retention

  17. Hard and Soft Decoding Hard Decoding Soft Decoding

  18. Different Block Lengths

  19. Asymmetric and Symmetric Errors

  20. Code Rate Switching Is repetitive code construction needed at rate-switching PECs? BER Correction Capability 0 PEC pec3 pec1 pec2 R1 R2 R2

  21. Why Code Reconstruction is Not Needed?

  22. With and Without Code Reconstruction Upper odd page Average

  23. Summary • On the flash data • Polar codes are comparable to LDPC codes using hard and soft sensing • Larger block lengths do not improve decoding performance a lot • More symmetric, better decoding performance • Repetitive code construction is not necessary for adaptive decoding

  24. Future Directions • Error floor performance • Comparing with LDPC decoder with the same hardware latency • Efficient hardware implementations Thank You

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