JTAG UART port in NIOS

1. JTAG UART port in NIOS

2. JTAG UART introduction • The JTAG UART core with Avalon interface implements a method to communicate serial character streams between a host PC and an SOPC Builder system on an Altera • JTAG UART core eliminates the need for a separate RS-232 serial connection to a host PC for character I/O • The core provides an Avalon interface that hides the complexities of the JTAG interface from embedded software programmers.

3. JTAG UART fundamental

4. Avalon Slave Interface and Registers • The JTAG UART core provides an Avalon slave interface to the JTAG circuitry on an Altera FPGA. The user-visible interface to the JTAG UART core consists of two 32-bit registers data and control accessed through an Avalon slave port. • Avalon master accesses the registers to control the core and transfer data over the JTAG connection. 8-bit units of data at a time; eight bits of the data register serve as a one-character payload. • The JTAG UART core provides an active-high interrupt output that can request an interrupt when read data is available, or when the write FIFO is ready for data

5. Read and Write FIFOs • The JTAG UART core provides bidirectional FIFOs to improve bandwidth over the JTAG connection • Read/write to JTAg UART data register will pop/push data into FIFO • Length: 64 Byte, width: 8-bit

6. Host-Target Connection

7. Instantiating the Core in SOPC Builder • Write FIFO Settings Depth: Depth: The write FIFO depth can be set from 8 to 32,768 bytes. IRQ Threshold: The write IRQ threshold governs how the core asserts its IRQ in response to the FIFO emptying Construct using registers instead of memory blocks: Turning on this option causes the FIFO to be constructed out of on-chip logic resources

8. Instantiating the Core in SOPC Builder • Read FIFO Settings Depth: Depth: The read FIFO depth can be set from 8 to 32,768 bytes. IRQ Threshold: The read IRQ threshold governs how the core asserts its IRQ in response to the FIFO emptying Construct using registers instead of memory blocks: Turning on this option causes the FIFO to be constructed out of on-chip logic resources

9. Software Programming Model • HAL library support • Communicate through HAL device driver • Programming in register-level

10. HAL System Library Support • Nios II programs treat the JTAG UART core as a character mode device, and send and receive data using the ANSI C standard library functions, such as getchar() and printf() • Example 5–1 demonstrates the simplest possible usage, printing a message to stdout using printf()

11. Header files needed • altera_avalon_jtag_uart.h This file have the declaration of HAL system library device driver

12. Setup I/O device in Nios IDE 3 default system I/O file devices in HAL, use BSP editor to assign character I/O ports to them

13. Example of using printf() for jtag uart output

14. Example of using printf() for jtag uart output #include “stdio.h” int main() { char c; scanf(“%c”,c); return 1; }

15. Connect JTAG UART with file I/O • JTAG UARG driver provided by HAL allows device I/O through file operation • Device name “/dev/jtag_uart_name” • Functions: Open, Close, Write, Read

16. Example of jtag uart I/O

17. I/O through register access • Low level I/O operation • Need fewer HAL support • Difficult to implement • Needed when writing device driver or programming without HAL support

18. Header files needed • altera_avalon_jtag_uart_regs.h This file defines the core's register map, providing symbolic constants to access the low-level hardware. The symbols in this file are used only by device driver functions

19. JTAG UART Register File

20. JTAG UART Register File

21. JTAG UART interrupts • The JTAG UART core has two kinds of interrupts: write interrupts and read interrupts. • The WE and RE bits in the control registe enable/disable the interrupts

22. JTAG UART interrupts • The read interrupt condition is set whenever the read FIFO has read_threshold or fewer spaces remaining • The write interrupt condition is set whenever the write FIFO has read_threshold or fewer spaces remaining

23. Read character from JTAG UART Step 1: Read data register c=IORD_ALTERA_AVALON_JTAG_UART_DATA(JTAG_UART_BASE) // read character from JTAG UART port Step 2: test valid bit c & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK // ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK= 0x00008000 Step 3: if valid, copy lower 8 bits (data) out c & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK;

24. Read character from JTAG UART While(1) { c=IORD_ALTERA_AVALON_JTAG_UART_DATA(JTAG_UART_BASE); if(c & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) { data=c & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK); break; } }

25. Send character to JTAG UART port IOWR_ALTERA_AVALON_JTAG_UART_DATA(JTAG_UART_BASE, data) Data will be sent to JTAG_UARG and received by Host PC terminal.

26. Variable Argument List • Function declaration usually looks like: Function (arg1,arg2,…arg n) • but some function has a special format, the argument list is not fixed until called • printf(“%d,%d,%s”,a,b,str)

27. Variable Argument List • How to implement function with variable argument list? • C convention: argument order in stack

28. Macro definition in stdarg.h typedef char* va_list; #define _va_start(ap,v)    ( ap = (va_list)_ADDRESSOF(v) + _INTSIZEOF(v) ) #define va_arg(ap,t)      ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) ) #define va_end(ap)        ( ap = (va_list)0 )

29. How to get var arg address ap points to nex var arg after call va_arg(ap,t) ap points to first var arg after va_start(ap,v)

30. Code sample #include “stdarg.h” void my_printf(char * arg, ...) { int i=0; int param_num=0; va_list ap; printf("number of param is %s\n",arg); param_num=atoi(arg); va_start(ap, arg); for(i=0;i<param_num;i++) { printf("The %dth param is %d\n",i+1,va_arg(ap,int)); } va_end(ap); }

31. Summary • JTAR UART on DE2 board • Introduction • HAL supports • Register file and register access • Interrupts • Data transmission through JTAG UART port • Variable argument lists