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Adding Support for swap to Multi Cycle Datapath

Adding Support for swap to Multi Cycle Datapath. You are to add support for a new instruction, swap that exchanges the values of two registers to the MIPS multicycle datapath of Figure 5.28 on page 323 swap $rs, $rt • Swap used the R-Type format with:

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Adding Support for swap to Multi Cycle Datapath

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  1. Adding Support for swap to Multi Cycle Datapath • You are to add support for a new instruction, swap that exchanges the values of two registers to the MIPS multicycle datapath of Figure 5.28 on page 323 swap $rs, $rt • Swap used the R-Type format with: the value of field rs = the value of field rd • Add any necessary datapaths and control signals to the multicycle datapath. Find a solution that minimizes the number of clock cycles required for the new instruction without modifying the register file. Justify the need for the modifications, if any. • Show the necessary modifications to the multicycle control finite state machine of Figure 5.37 on page 338 when adding the swap instruction.

  2. T F In the simple MIPS processor we studied, the “sign-extend” serves to • convert a 16-bit offset to a 32-bit number to add to the contents of a register. • T F A single cycle implementation of the MIPS processor requires that a single memory be used for both instructions and data. • T F A multiplexor with a 32-bit output can be implemented as a collection of 32 multiplexors with 1-bit outputs • T F The number of rows of a truth table depends on the number of inputs, not • the number of outputs. • T F The MIPS slt instruction only works correctly if both operand registers • contain non-negative values. • T F A 32-bit immediate value cannot be placed in a register by a single • instruction on the MIPS processor described in the book. • T F A 32-bit value in memory cannot be loaded into a register by a single • instruction on the MIPS processor described in the book. • T F The Bnegate line is connected to the carry-in line of each 1-bit ALU within • a 32-bit ALU. • T F On the MIPS computer, a jump instruction can use a wider range of immediate addresses than a branch instruction because more bits are allocated for the address in the jump instruction than the branch instruction.

  3. Calculate CPI (cycles per instruction) for the following situation. Assume the following instruction mix: 15% loads, 20% stores, 15% branches, and 50% arithmetic instructions. Here, loads take 5 cycles, stores take 4 cycles, branches take 2 cycles, and other instructions take 3 cycles

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