1 / 23

Modulo-N Counters

Modulo-N Counters. Lecture L8.4 Section 8.2. Counters. Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter . State Q2 Q1 Q0 Q2.D Q1.D Q0.D. D . Q . Q0.D. Q0. CLK . !Q. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1

kalani
Télécharger la présentation

Modulo-N Counters

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Modulo-N Counters Lecture L8.4 Section 8.2

  2. Counters • Modulo-5 Counter • 3-Bit Down Counter with Load and Timeout • Modulo-N Down Counter

  3. State Q2 Q1 Q0 Q2.D Q1.D Q0.D D Q Q0.D Q0 CLK !Q s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 0 0 0 s5 1 0 1 X X X s6 1 1 0 X X X s7 1 1 1 X X X D Q Q1.D Q1 CLK !Q D Q Q2.D Q2 CLK !Q Modulo-5 Counter

  4. State Q2 Q1 Q0 Q2.D Q1.D Q0.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 0 0 0 s5 1 0 1 X X X s6 1 1 0 X X X s7 1 1 1 X X X Modulo-5 Counter Q1 Q0 00 01 11 10 Q2 1 0 X X X 1 Q2.D Q2.D = Q1 & Q0

  5. State Q2 Q1 Q0 Q2.D Q1.D Q0.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 0 0 0 s5 1 0 1 X X X s6 1 1 0 X X X s7 1 1 1 X X X Modulo-5 Counter Q1 Q0 00 01 11 10 Q2 1 1 0 X X X 1 Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0

  6. State Q2 Q1 Q0 Q2.D Q1.D Q0.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 0 0 0 s5 1 0 1 X X X s6 1 1 0 X X X s7 1 1 1 X X X Modulo-5 Counter Q1 Q0 00 01 11 10 Q2 1 1 0 X X X 1 Q0.D Q0.D = !Q2 & ! Q0

  7. mod5cnt.abl MODULE mod5cnt TITLE 'Modulo-5 Counter' DECLARATIONS hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]); d7R FUNCTIONAL_BLOCK hex7seg; " INPUT PINS " CLK PIN 12; " 1 Hz clock (jumper) clear PIN 11; " switch 1 " OUTPUT PINS " Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED 14..16 Q = [Q2..Q0]; " 3-bit output vector [a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display

  8. mod5cnt.abl (cont’d) EQUATIONS Q.AR = clear; Q.C = CLK; Q2.D = Q1 & Q0; Q1.D = !Q1 & Q0 # Q1 & !Q0; Q0.D = !Q2 & !Q0; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.[D2..D0] = Q; d7R.D3 = 0; Note Asynchronous Clear

  9. mod5cnt.abl (cont’d) test_vectors(CLK -> Q) .C. -> 1; .C. -> 2; .C. -> 3; .C. -> 4; .C. -> 0; .C. -> 1; .C. -> 2; .C. -> 3; .C. -> 4; .C. -> 0; .C. -> 1; .C. -> 2; END

  10. Mod5cnt Simulation

  11. Counters • Modulo-5 Counter • 3-Bit Down Counter with Load and Timeout • Modulo-N Down Counter

  12. State Q2 Q1 Q0 Q2.D Q1.D Q0.D D Q Q0.D Q0 CLK !Q s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 D Q Q1.D Q1 CLK !Q D Q Q2.D Q2 CLK !Q 3-Bit Down Counter

  13. State Q2 Q1 Q0 Q2.D Q1.D Q0.D s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 3-Bit Down Counter Q1 Q0 00 01 11 10 Q2 1 0 1 1 1 1 Q2.D Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0

  14. State Q2 Q1 Q0 Q2.D Q1.D Q0.D s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 3-Bit Down Counter Q1 Q0 00 01 11 10 Q2 1 1 0 1 1 1 Q1.D Q1.D = !Q1 & !Q0 # Q1 & Q0

  15. State Q2 Q1 Q0 Q2.D Q1.D Q0.D s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 3-Bit Down Counter Q1 Q0 00 01 11 10 Q2 1 1 0 1 1 1 Q0.D Q0.D = ! Q0

  16. dncnt3ld.abl MODULE dncnt3ld TITLE '3-bit Down Counter with Clear and Load' DECLARATIONS hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]); d7R FUNCTIONAL_BLOCK hex7seg; " INPUT PINS " CLK PIN 12; " 1 Hz clock (jumper) clear PIN 11; " switch S6:1 load PIN 7; " switch S6:2 D2..D0 PIN 4,3,2 ISTYPE 'com'; " switch S7:1-3 D = [D2..D0]; " 3-bit input " OUTPUT PINS " Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED 14..16 Q = [Q2..Q0]; " 3-bit output vector LED9, LED10 PIN 35,36 ISTYPE 'com'; " LED 9,10 timeout PIN 37 ISTYPE 'com'; " LED 11 [a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display If load = 1, Load D to [Q2..0] timeout = 1 when [Q2..0] = [0,0,0]

  17. dncnt3ld.abl (cont’d) EQUATIONS LED9 = clear; LED10 = load; Q.C = CLK; Q.AR = clear; WHEN load THEN Q.D = D; ELSE { Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0; Q1.D = !Q1 & !Q0 # Q1 & Q0; Q0.D = !Q0; } timeout = !Q0 & !Q1 & !Q2; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.[D2..D0] = Q; d7R.D3 = 0; If load = 1, Load D to [Q2..0] Down counter equations timeout = 1 when [Q2..0] = [0,0,0]

  18. dncnt3ld.abl (cont’d) test_vectors([CLK, clear, load, D] -> [Q, timeout]) [.c.,1,0,0] -> [0,1]; [.c.,0,0,0] -> [7,0]; [.c.,0,0,0] -> [6,0]; [.c.,0,0,0] -> [5,0]; [.c.,0,0,0] -> [4,0]; [.c.,0,0,0] -> [3,0]; [.c.,0,1,5] -> [5,0]; [.c.,0,0,0] -> [4,0]; [.c.,0,0,0] -> [3,0]; [.c.,0,0,0] -> [2,0]; [.c.,0,0,0] -> [1,0]; [.c.,0,0,0] -> [0,1]; [.c.,0,0,0] -> [7,0]; END

  19. dncnt3ld Simulation

  20. Counters • Modulo-5 Counter • 3-Bit Down Counter with Load and Timeout • Modulo-N Down Counter

  21. 3-Bit Down Counter with Load and Timeout To make a modulo-N counter, load I2..I0 with N-1 when timeout = 1

  22. modndcnt.abl (modified dncnt3ld.abl) EQUATIONS LED9 = clear; LED10 = load; Q.C = CLK; Q.AR = clear; WHEN (load # timeout) THEN Q.D = D; ELSE { Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0; Q1.D = !Q1 & !Q0 # Q1 & Q0; Q0.D = !Q0; } timeout = !Q0 & !Q1 & !Q2; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.[D2..D0] = Q; d7R.D3 = 0; If timeout = 1, Load D to [Q2..0] Down counter equations timeout = 1 when [Q2..0] = [0,0,0]

  23. Modulo-5 Counter [D2..D0] = [1,0,0]

More Related