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Single Event Effects of a FLASH-based FPGA

Single Event Effects of a FLASH-based FPGA. J. J. Wang, Brian Cronquist, John McCollum Actel Corporation Rich Katz, Igor Kleyner (OSC) - NASA/GSFC Rocky Koga - Aerospace. Outline. Device and Technology Architecture Beam Tests and Results Conclusions. ProASIC.

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Single Event Effects of a FLASH-based FPGA

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  1. Single Event Effects of a FLASH-based FPGA J. J. Wang, Brian Cronquist, John McCollum Actel Corporation Rich Katz, Igor Kleyner (OSC) - NASA/GSFC Rocky Koga - Aerospace

  2. Outline • Device and Technology • Architecture • Beam Tests and Results • Conclusions JJ Wang SEE02

  3. ProASIC ProASIC is a register rich FLASH-based FPGA family manufactured by 0.25µm technology and offering up to half million system gates. JJ Wang SEE02

  4. ProASIC Plus ProASIC Plus is an improved ProASIC manufactured by 0.22µm technology and above, offering up to 1M system gates. JJ Wang SEE02

  5. FPGA Switch Technology • SEE of FLASH-based FPGA comes only from its CMOS logic. *In operation mode, not programming mode JJ Wang SEE02

  6. The FLASH Switch PRG/SEN SWITCH WORD LINE SEL1 SEL2 The switch is comprised of two transistors which share a gate. Additional source/drain implant in PRG/SEN device enables tunneling to overlapping floating gate. ONO inter-poly dielectric JJ Wang SEE02

  7. Program and Erase 5V 5V “Programming” -11.5V 0V 0V “Erasing” 16.5V Program and erase are accomplished with F-N Tunneling where the floating gate overlaps the source and drain. JJ Wang SEE02

  8. Operation 1.25V 1.25V 1.5VCC “On state” 2.5V 1.25V 1.25V < 0V “Off state” 2.5V During operation, the floating gate is effectively 1.5VCC in the on state and slightly negative in the off state. JJ Wang SEE02

  9. Comparison with SRAM Switch Switch & Routing Memory Cell Switch & Routing Memory Cell The FLASH switch is approximately 1/7th the area of an SRAM switch. SRAM based PLD FLASH based PLD 7 : 1 JJ Wang SEE02

  10. Outline • Device and Technology • Architecture JJ Wang SEE02

  11. Chip Layout Basic SRAM or FIFO Block 256 x 9 Core Logic Cell ProASIC contains standard elements of any FPGA: Logic Cells, IO, Embedded SRAM and Routing Resources JJ Wang SEE02

  12. Logic Tile L7 0 1 L10 YL F2 L11 I8 1 0 (long) (local) (X3) L9 L8 Pin 4 Data L4 I5 L5 (X2) L6 Pin 3 L2 L0 L3 L1 L15 L12 L14 L13 CLK I2 (X1) Pin 2 1 to 8 gates Set/Reset The ProASIC logic tile is a fine grained FPGA. Configured with switches. Primitive register with set/reset or 3-input combinatorial function. Low cost of registers ideal for registers filtering applications. JJ Wang SEE02

  13. ProASIC Routing Resources 1 4 Global Signals 2 High Speed Bus Lines 4 Ultra Fast Local Lines Efficient Long Lines 3 ProASIC has 4 distinct classes of routing resources. • Four high-speed global paths • High-performance routing hierarchy • Corner-to-corner delay< 4ns (typical) JJ Wang SEE02

  14. Global Routing ProASIC has flexible global resources. Accessible from 4 pads. Used for clocks, sets/resets and other high fanout nets. 4 H-trees. 3.5ns delay. 0.25ns skew Tree junctions controlled by switch. JJ Wang SEE02

  15. Example of Global Distribution Unused branches of the global network are disconnected from the network, saving power. JJ Wang SEE02

  16. High Speed Bus Lines Bus network designed for processor-based functionality. 24 Lines 24 Lines 24 Lines 24 Lines 24 Lines 24 Lines 24 Lines 24 Lines 24 Lines 24 Lines 8 Lines JJ Wang SEE02

  17. Local Routing L L L L L L L L L L L L L L L L L L L L X X X X X X X X X X X X X X X X X X X X X X X X X X X Efficient Long Lines (1, 2 or 4 Tiles long) Connection to logic cell inputs Inputs Ultra Fast Local Lines to 8 surrounding Tiles Output Intrinsic Cell + Wire Delay < 0.5ns (Typical) JJ Wang SEE02

  18. IO Functionality 3.3V 2.5V ProASIC 2.5V Core, 2.5V and 3.3V I/Os 3.3V Device 2.5V Device TTL/CMOS Levels Pull-up Control EN Y A Pad Drive Strength and Slew Rate Control Individually Selectable 3.3V & 2.5V I/Os 3.3V 33MHz PCI Compliant Individually Selectable Slew Rate Control: 25, 50, 100mA/nsec JJ Wang SEE02

  19. Outline • Device and Technology • Architecture • Beam Tests and Results JJ Wang SEE02

  20. Heavy Ion Test Results: • SEL detected, 16.2 < LETth < 22.9MeV-cm2/mg. • SEU cross-section at 16.2MeV-cm2/mg is 9.6 x 10-8 cm2/bit. • No detectable FLASH switch upset. JJ Wang SEE02

  21. Heavy Ion Test Results: JJ Wang SEE02

  22. Proton Test Results: • No SEL JJ Wang SEE02

  23. Configuration Switch SEU 2.5 V 0 – 2.5V 0 – 2.5V 3.75V N+ N+ On-state P-Well 0V 2.5 V 0 – 2.5V 0 – 2.5V > -1V N+ N+ P-Well 0V Off-state The FLASH switch is intrinsically SEU hard. DQ/Q < 3% for LET = 100MeV-cm2/mg Total dose effect can be counteracted by periodically refreshing the device. JJ Wang SEE02

  24. SEE during Configuration -11.5 V 5 V 5 V N+ N+ P-Well “Programming” 16.5 V 0 V 0 V N+ N+ “Erasing” P-Well The switch is susceptible to gate rupture during configuration (high voltage across thin oxide) which may limit effectiveness for “reconfigurable payloads.” Configuration not required for conventional FPGA applications. Peripheral high voltage (programming) circuits maybe susceptible to latch-up. JJ Wang SEE02

  25. Conclusions • ProASIC offers a high-density, re-programmable, and non-volatile programmable logic solution to high reliability market. • However, at this moment: • ProASIC is not suitable for space-flight application due to its SEL sensitivity at moderate LETTH. • But for avionics, the heavy ion and proton testing data show that it is immune to neutrons. JJ Wang SEE02

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