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COMP541 More on Registers and Counters

COMP541 More on Registers and Counters. Montek Singh Feb 20, 2012. Today ’ s Topics. Registers Counters. Registers and Counters: Definitions. Register – a set of flip-flops May include extensive logic to control state transition May allow shifting

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COMP541 More on Registers and Counters

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  1. COMP541More on Registers and Counters Montek Singh Feb 20, 2012

  2. Today’s Topics • Registers • Counters

  3. Registers and Counters: Definitions • Register – a set of flip-flops • May include extensive logic to control state transition • May allow shifting • register also refers to fast memory for storing data in a computer • Counter • Register that goes through sequence of states as it is clocked

  4. Simple Register • Behavior • on positive edge of clock… • store D  becomes Q • “Clear” signal asserted low • power-up reset

  5. Clocking • Typically don’t want to load every clock • What to do? • How about temporarily gating (i.e., freezing) the clock? • adds skew (i.e., delay) to clock • can be a problem if neighboring registers “hear” the clock at different times

  6. Enable • Better solution: • use an “enable” • if Load is high • then D goes through • else Q is fed back • keep same value • No clock gating! • Did this because D flipflop doesn’t have a “no change” behavior

  7. Counters • Counter is a register – has state • Also goes through sequence of states – counts – on clock or other pulses • Binary counter • Counts through binary sequence • n bit counter counts from 0 to 2n

  8. Ripple Counter • Simple • So Q will alternate 1 and 0 • Why called ripple counter?

  9. Synchronous Counters • Ripple counter is easy • rippling nature may cause problems, though • delay increases with bit width! • Synchronous counter most common • meaning every flip-flop is driven by the same clock

  10. Synchronous Counter • Same clock fed to all flip-flops • But… • delay again increases with bit width

  11. Parallel Design • Now “constant” delay • higher order bits need gates with more fan-in though • Can gang these to make longer serial-parallel counter

  12. Verilog Counter (simple) module count (CLK, EN, Q); input CLK, EN; output [3:0] Q; reg [3:0] Q; always@(posedge CLK) begin if (EN) Q <= Q + 4'b0001; end endmodule

  13. Verilog Counter (from book) module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] Q; assign CO = (count == 4'b1111 && EN == 1’b1) ? 1 : 0; always@(posedge CLK or posedge RESET) begin if (RESET) Q <= 4'b0000; else if (EN) Q <= Q + 4'b0001; end endmodule

  14. Arbitrary Count • One more type of counter is useful • Count an arbitrary sequence • maybe you need a sequence of states • maybe a pseudo-random sequence

  15. Circuit and State Diagram

  16. Shift Registers • Capability to shift bits • In one or both directions • Why? • Part of standard CPU instruction set • Cheap multiplication • Serial communications • Just a chain of flip-flops

  17. Simple 4-Bit Shift Register • Clocked in common • Just serial in and serial out • Is this a FIFO?

  18. Verilog for Simple 4-bit Shift Register module srg_4_r (CLK, SI, Q, SO); input CLK, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; always@(posedge CLK) begin Q <= {Q[2:0], SI}; end endmodule

  19. Symbol • How about enabling/disabling? • We could gate the clock • But have to potentially deal with skew • Usually an enable provided

  20. Parallel Load • Can provide parallel outputs from flip-flops • And also parallel inputs

  21. Schematic Detail Next

  22. Detail

  23. Why is this useful? • Basis for serial communications • Keyboard • Serial port • Initially to connect to terminals • Now mainly for modem • USB • Firewire

  24. Example Could shift data in, or parallel load What’s on wire at each clock? Clocked 4 times

  25. Table Showing Shift

  26. Serial vs. Parallel Transfer • Parallel transfer – over as many wires as word (for example) • Serial transfer – over a single wire • Trade time for wires • Takes n times longer • although lately, may have speed advantages over parallel in very high-speed scenarios • e.g., USB (Universal Serial Bus)

  27. Bidirectional Shift Register • Shift either way • Now we have following possible inputs • Parallel load • Shift from left • Shift from right • Also “no change” • Schematic next

  28. Schematic

  29. Next Class • Lab problem: How to generate a VGA signal • Timing of sequential logic • Then on to • Arithmetic circuits • Memories

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