Introduction to Embedded Systems

1. Introduction to Embedded Systems Rabie A. Ramadan rabieramadan@gmail.com http://www.rabieramadan.org/classes/2014/embedded/ 6

2. Real Time Systems

3. Correctness of the system may depend not only on the logical result of the computation but also on the time when these results are produced Tasks attempt to control events or to react to events that take place in the outside world These external events occur in real time and processing must be able to keep up Processing must happen in a timely fashion, neither too late, nor too early Some examples include, Air Traffic Control, Robotics, Controlling Cars/Trains, Medical Support, Multimedia. Real Time Systems

4. Hard real time systems Must always meet all deadlines System fails if deadline window is missed Soft real time systems Must try to meet all deadlines System does not fail if a few deadlines are missed Firm real time systems Result has no use outside deadline window Tasks that fail are discarded Types of Real Time Systems

5. Real time tasks Periodic - Each task is repeated at a regular interval - Max execution time is the same each period - Arrival time is usually the start of the period - Deadline is usually the end Aperiodic - Each task can arrive at any time

6. Determines the order of real time task executions Dynamic vs. Static Dynamic schedule computed at run-time based on tasks really executing, priorities computed on the fly Static schedule done at compile time for all possible tasks, priorities are already known Real-Time Scheduling

7. Simplest type of real time scheduling - Tasks are periodic, with hard deadlines - Tasks are completely independent and do not communicate with each other - Tasks are scheduled according to priority and task priorities are fixed - Computation time is known and constant Rate Monotonic

8. Rate Monotonic • Higher priorities usually assigned to tasks with smaller periods • If t(h) < t(l), then PR(h) > PR(l), where t indicated period and PR indicates the priority. This is called rate monotonic priority assignment. • Calculates the critical instant for each task. • Occurs when task Ti and all higher priority tasks are scheduled simultaneously • If tasks deadline scheduled at critical instant, then the task can always meet its deadline.

9. Deadline Monotonic Tasks with shorter deadlines get higher priority. Static Scheduling. If D(h) < D(l), then PR(h) > PR(l), where D indicates the deadline. This is called Deadline Monotonic priority assignment.

10. Dynamic Scheduling Assume a preemptivesystem with dynamic priorities Like deadline monotonic, the task with shortest deadline gets highest priority, but the difference is real time priorities can vary during the system’s execution. Priorities are reevaluated when events such as task arrivals, completions occur EDF: Earliest Deadline First

11. Real Time Synchronization • Required when tasks are not independent and need to share information and synchronize • If two tasks want to access the same data, semaphores are used to ensure non-simultaneous access. • Potential Issues • Priority Inversion– A situation in which a higher priority job is blocked by lower priority jobs for an indefinite period of time • Chain Blocking– A situation in which more than two resources are available and a high priority task is blocked off from both because of two or more lower priority tasks holding locks on one or both of the resources.

12. Priority Inversions • Low priority task holds resource that prevents execution of higher priority tasks. - Task L acquires lock - Task H needs resource, but is blocked by Task L, so Task L is allowed to execute - Task M preempts Task L, because it is higher priority - Thus Task M delays Task L, which delays Task H

13. Chained Blocking: Problem of PIP In the worst case, the highest priority task T1 can be blocked by N lower priority tasks in the system when T1 has to access N semaphores to finish the execution! Source of the figure: DamirIsovic, Malardaren University, Sweden

14. Priority Inheritance Protocol • PIP eliminates priority inversion problem • The algorithm will increase the priority of a task to the maximum priority of any task waiting for any resource the task has a resource lock on - i.e. if a lower priority task L has a lock on a resource required by a higher priority task H, then the priority of the lower task is increased to the priority of the higher task - Once the lock is released the task resumes back its original priority.

15. Priority Ceiling Protocol • Each resource is assigned a priority ceiling, which is a priority equal to the highest priority of any task which may lock the resource. • PCP eliminates chain blocking which considers the use of more than one resource or semaphore • A task can acquire a lock on resource S only if no other task holds a lock on resource R. Thus higher priority tasks will not be blocked through both S and R • If a high priority task is blocked through a resource, then the task holding that resource gets the priority of the high priority task. Once the resource is released, the priority is reset back to its original

16. Timers and Interrupts

17. The tight-coupling between the computer and external world distinguishes an embedded system from a regular computer system. synchronizationbetween the executing software and its external environment is critical for the success of an embedded system.  Synchronization

18. Definition of ‘Interrupt’ Event that disrupts the normal execution of a program and causes the execution of special instructions

19. Interrupts Interrupt Program time t

20. Interrupts Interrupt Program Program Interrupt Service Routine time t

21. Interrupts Interrupt Program Program Save Context Restore Context Interrupt Service Routine mul R1, 9 mov R1, cent eg push R1 eg pop R1 time t

22. Hardware event is called a trigger. The hardware event can either be a busy to ready transition in an external I/O device (like the UART input/output) or an internal event (like bus fault, memory fault, or a periodic timer). The execution of the interrupt service routine is called a background thread. The thread is killedwhen the interrupt service routine returns from interrupt  A new thread is created for each interrupt request.  Trigger

23. Threads share: Access to I/O devices, System resources, Global variables, Processeshave separate: global variables and system resources. Processes do not share I/O devices. Threads and Processes

24. Exception and Interrupt Handling in ARM as a Case Study

25. Pollingmechanism wastes the CPU time in looping forever checking some flags to know that the event occurred. We have nowadays systems with more than one interrupt source. We may need priorities to be assigned to different Events Interrupt is the best way to handle events Interrupts vs. Polling

26. Internally has 7 different modes of operation User mode: used for normal program execution state Fast Interrupt Request (FIQ) mode: This mode is used for interrupts requiring fast response and low latency. like for example data transfer with DMA Interrupt Request (IRQ) mode: used for general interrupt services Abort mode: selected when data or instruction fetch is aborted System mode: Operating system privilege mode for users Undefined mode: When undefined instruction is fetched Supervisor mode: used when operating system support is needed where it works as protected mode ARM modes of operation

27. Protected mode differed from the original mode: Later dubbed “real mode”, Areas of memory could be physically isolated by the processor itself to prevent illegal writes to other programs running in memory at the same time. Prior to protected mode, multiple programs could be running in memory at the same time, but any program could access any area of memory and, therefore, if malicious or errant, for example, could take down the entire system. Isolates that possibility by allowing the operating system (OS) to dictate where each program should run. Protected Vs. Original Mode

28. ARM Modes of Operation

29. Register structure in ARM depends on the mode of operation. There are 16 (32-bit) registers named from R0 to R15 in ARM mode (usr). Registers R0 to R12 are general purpose registers, R13 is stack pointer (SP), R14 is subroutine link register R15 is program counter (PC). R16 is the current program status register (CPSR) and it plays a main role in the process of switching between modes – eg. the current processor mode ARM Register set

30. Some registers are available with the same name but as another physical register in memory which is called (banked) Decreases the effort needed when context switching is required The new mode has its own physical register space and no need to store the old mode’s register values Banked Registers

31. Register Organization in ARM

32. Exception : any condition that needs to halt normal execution of the instructions. State of resetting ARM core, Failure of fetching instructions or memory access There is always software associated with each exception, Exception handler. Each of the ARM exceptions causes the ARM core to enter a certain mode automatically. Ex. ARM Exceptions

33. A table of instructions that the ARM core branches to when an exception is raised. These instructions are places in a specific part in memory and its address is related to the exception type Vector Table

34. Since exceptions can occur simultaneously We may have more than one exception raised at the same time, The processor has to have a priority for each exception so it can decide which of the currently raised exceptions is more important Exception priorities

35. Various exceptions that occur on the ARM and their associated priorities. Exception priorities Both are caused by an instruction entering the execution stage of the ARM instruction pipeline

36. This register is used to return the PC to the appropriate place in the interrupted task not always the old PC value. ???????? It is modified depending on the type of exception. In the case of IRQ exception, the link register is pointing initially to the last executed instruction In data abort exception , the exception is handled and the PC should point to the same instruction again to retry accessing the same memory location again. Data Exception : processor can fetch and store data or they can refuse to do either. Link Register

37. Save the address of the next instruction in the appropriate Link Register (LR). Copy Current Program Status Register (CPSR) to the Saved Program Status Register (SPSR) of new mode. Change the mode by modifying bits in CPSR. Fetch next instruction from the vector table. Entering and exiting an exception handler

38. Move the Link Register LR to the PC. Copy SPSR back to CPSR, this will automatically changes the mode back to the previous one. Clear the interrupt disable flags (if they were set). Leaving exception handler

39. Interrupts

40. Interrupts

41. Interrupts

42. Interrupt handling schemes

43. Interrupt handling schemes

44. Interrupt handling schemes

45. Interrupt handling schemes

46. In class work

49. Assignment- Thursday 24thWrite a 4 pages report on Embedded System Software profiling Methods or embedded system testing methodology?Prepare a presentation for about 20 minutes .