Regional Calorimeter Trigger

1. Regional Calorimeter Trigger • Outline: • Status of Prototypes • Plans for Production Testing • Plans for Integration, Chain and Slice Tests • Schedule and Milestones RCT Personnel: Faculty: S. Dasu, W. H. Smith Physicists: P. Chumney, Monika Grothe (New) Students: C. Hogg (UG) Engineers: T. Gorski (Lead Engineer), M. Jaworski, P. Robl (Physical Sciences Laboratory),J. Lackey (Retired, July 2003) Technician: R. Fobes

2. Algorithms

3. Overview

4. Calorimeter Geometry EB, EE, HB, HE map to 18 RCT crates Provide e/g and jet, t, ET triggers

5. Trigger Mapping

6. 160 MHz point to point backplane (prototype tested) 18 Clock&Control (prototype tested), 126 Electron ID (prototype tested),18 Jet/Summary Cards -- all cards operate @ 160 MHz Use 5 Custom Gate-Array 160 MHz GaAs Vitesse Digital ASICs Phase, Adder, Boundary Scan, Electron Isolation, Sort (manufactured) Spares not included* Calorimeter Trigger Crate • Data from calorimeter FE on Cu links@ 1.2 Gbaud • Into 126* rearReceiverCards • Prototypetestedw/ ASICs

7. First Full RCT Crate • 18 Such Crates make up the full RCT System covering |h|<5 & 0 < f < 2p. Rear: Receiver Cards Front: Electron, Jet, Clock Cards

8. Second Generation Crate & Backplane • 160 MHz with 0.4 Tbit/sec dataflow (point-to-point) • Tests indicate good signal quality • Designed to incorporate all algorithms • Non-Isolated Electron, Tau & Jet Trigger primitives • Most data paths checked manually and with JTAG, and with loop-back cables. VME 48V externally supplied VME Power Supply Std. VME Slots Custom Point-to-point Dataflow Custom Point-to-point Dataflow Rear Front

9. Second Generation Clock & Control Card • Fans out 160 MHz clock & adjusts phase to all boards • Design validated - With small changes, layout and routing of production version completed - Ready for full production. Clock delay adjust DC-DC Converters

10. Second Generation Receiver Card • Full featured board & Phase, Boundary Scan & Adder ASICS fully validated. Production Started (ASIC production finished). • Eight Boards built and tested in full crate test. • Full quantity of mezzanine link cards (1422) are manufactured. Adder PHASE ASICs mezz link cards MLUs BSCAN ASICs DC-DC Top side with 1 of 8 mezzanine cards & 2 of 3 Adder ASICs Bottom side with all Phase& Boundary Scan ASICs

11. Compact MezzanineCards for each Receiver Card accept 4 x 20 m 1.2-Gbaudcopper pairs transmitting 2 cal. tower energies every 25 ns with low cost & power. Uses Vitesse Link Chips (7216-01). Final Serial Link Test Card (STC) Status: Already commissioned, cables, cards, 48V PS, and support software, delivered to CERN in March, operating in ECAL Electronics lab stably with no errors for months. Delivered to Princeton for HCAL tests in June and operating stably with no errors since. Two pairs in use @ UW for testingreceiver mezzanine cards. RCT 4 x 1.2 Gbaud CopperLink Cards & Serial Test Card

12. EISO SORT ASICs EISO Second Generation Electron Isolation Card • Full featured final prototype board is fully validated - production underway • 8 boards made and tested as part of full crate test. • Electron ID & Sort ASICs validated and production complete

13. Jet/Summary Card • Full function prototype manufactured and tested. • Uses SORT ASICs to find top four e/g, threshold for muon bits, both to GCT • Region energies to GCT • Absorbs HF functionality with Rec. Mezz. Card, HF sent to GCT. • Integration test with GCT Done - Change in termination - Production to start shortly Receiver Mezz. Card Phase ASIC Backplane: Two e/gper region.Region ET Sums Cables To GCT BSCAN ASICs Sort ASICs BSCAN ASICs

14. RCT Test Suites • Receiver Card (~150) • Cycle memory at speed - all paths beyond Phase ASIC exercised • JTAG to test some circuits in detail • A fraction of inputs (4 - 8) from STC transmitters • Covers full data path • Electron Isolation Card (~150) • Input by cycling RC memories • Multiple cards (corner data by loop back cables) • JTAG to test some circuits in detail • Jet/Summary Card (~20) • Input by cycling RC memories • Full crate with RCs + EICs used • HF path test using STC transmitter • Output to Jet Capture Card for testing (in design)

15. Software Work • Crate Processor Hardware & Software • Present status: Old MVME Processor and software • Needs replacement by new CMS Compatible System • New Hardware & New Software • Software for debugging production boards • Developing diagnostics software for each board • Ship data for analysis outside crate processor • Use tools well known to physicists • Final software (in XDAQ) - Design work beginning • Want to reuse as much of test software as possible • Need to add CMS Interfaces • Software will be integrated with CMS Online code for operations • Monitoring/controls, diagnostics, configuration downloading and documentation, modeling, physics simulation, etc. • Personnel • P. Chumney, S. Dasu, M. Grothe

16. Production Testing Tasks:2003 - 2005 • Testing software • VME Code + Conversion to SBS - S. Dasu, P. Chumney • RC & EIC Test Suites (JTAG…) well underway - P. Chumney • Jet/Summary Output verification code - M. Grothe • Integration of test software in XDAQ - P. Chumney, M. Grothe • Mezzanine cards (2003) • 4 months to test ~1400 cards - M. Jaworski & M. Grothe • Full Board Production & Test (2004-2005): • ~ 150 each Receiver & Electron Cards, ~ 20 each Jet, Clock Cards, Backplanes & Crates need testing - All • Repair & Inventory - R. Fobes • Test full crates for delivery (2005) • 1 year for testing full complement of crates - all • Use custom card to capture output of J/S - Jet Capture Card - Under design - T. Gorski • Provides trigger for slice test

17. Integration and Chain Tests • Integration Tests (2003) • Serial Test Cards for input link tests • 1 pair at CERN for ECAL integration since March. • 1 pair at Princeton for HCAL integration since June. • Remaining 6 are being used for receiver mezzanine card production testing at UW • Will be reused to pump data to RCT for full test (2005) • Pre-production Prototype Full Crate tests • Global Calorimeter Trigger (Bristol group) integration at Madison in August is successful - Termination scheme agreed - Minor changes to UW JSC and Bristol IC • Integration Tests (2004) • Augment above tests with additional electronics from ECAL, HCAL, & GCT groups as becomes available. • Initiate Slice Test

18. Slice Tests and Trigger Commissioning • Slice Tests (Starting Late Summer 2004) • Use full crate of tested production boards • Will remain at CERN as spare boards and crate • JSC Output Capture Card provides test trigger • Personnel: • M. Grothe moves to CERN, assisted with visits by others • Trigger Commissioning (Starting April, 2005) • All eighteen crates - fully tested and shipped to CERN • All electronics rechecked in electronics test facility • Full commissioning underground in USC55 • Personnel: • When production finishes, P. Chumney moves to CERN to join M. Grothe, assisted with visits by others.

19. RCT Conclusions • Regional Calorimeter Trigger • All pre-production prototype boards and ASICs built & validated • All boards, ASICS, & crates are either produced, in production or about to start production • Integration tests w/ECAL,HCAL, GCT have started • Very good progress, but… • Major work from now on: • Production Testing of ~1800 Boards • Software Development - Integration with XDAQ • Slice Test Preparation + Software • Installation and Commissioning • Operations! • We have the team in place to do the job!