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wwwhephy.oeaw.ac.at/p3w/cms/trigger

Luminosity and the Global Trigger. http://wwwhephy.oeaw.ac.at/p3w/cms/trigger. Vienna Group. A. Taurok, I. Magrans de Abril, C.-E. Wulz. Presented by Claudia-Elisabeth Wulz. Discussion Meeting on Luminosity CERN, 9 May 2006. PSB (Pipelined Synchronizing Buffer) Input and Synchronisation

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wwwhephy.oeaw.ac.at/p3w/cms/trigger

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  1. Luminosity and the Global Trigger http://wwwhephy.oeaw.ac.at/p3w/cms/trigger Vienna Group A. Taurok, I. Magrans de Abril, C.-E. Wulz Presented by Claudia-Elisabeth Wulz Discussion Meeting on Luminosity CERN, 9 May 2006

  2. PSB (Pipelined Synchronizing Buffer) Input and Synchronisation GMT (Global Muon Trigger) Global Muon Trigger logic GTL (Global Trigger Logic) Algorithm logic FDL (Final Decision Logic) Level-1 Accept decision GTFE (Global Trigger Frontend) Readout TCS (Trigger Control System Module) Central Trigger Control L1A_OUT (Level-1 Accept Module)Distribution of Level-1 Accept CONV6U (Conversion Boards) Reception of status signals from the subsystems TIM (Timing Module) Timing Global Trigger Crate

  3. Final Decision Logic (FDL) Board

  4. FDL functionality • The Final Decision Logic (FDL) board receives 128 algorithm bits from the Global Trigger Logic (GTL) board and 64 Technical Trigger bits from a dedicated Pipeline Synchronizing Buffer input board (PSB0). • 8 Final OR’s are available (only 1 in normal running). • A mask (also a veto mask for technical triggers if required) is applied to the 128 + 64 algorithm bits to determine the Final OR’s. • The Final OR’s go to the Trigger Control System (TCS) board, which delivers the L1A signals to the front-end electronics through two L1AOUT boards.

  5. FDL block diagram • Rate counters monitor each trigger algorithm bit and prescalers downscale the average rate if required (maximum reduction factor 216 = 65536, down to 600 Hz). Each algo and technical trigger bit first goes to the corresponding prescaler. Each prescaled trigger bit then goes to a rate counter and the ring buffer for readout.

  6. FDL Rate counters • 128 rate counters for physics triggers • 64 rate counters for technical triggers • All these counters are currently 16-bit, which overflow after 0.6 s at 100 kHz. A mimimal number of 32-bit counters, which overflow after 11.9 h at 100 kHz, could be implemented for algorithms used for luminosity measurement. How many depends on space of the chip. TBD! • Rate counters stop at ‘FFFF’. The update period of these counters is programmable (8 possible values from 10-5 s to 105 s). Each time a counter is reset its value is moved to the RATE_COUNTER register, which can be read out through VME. The values will be stored in the Conditions Database, and should be accessible for monitoring from there.

  7. L1AOUT, TCS

  8. TCS functionality • The central Trigger Control System (TCS) board controls instantaneous and average L1A rates according to: • trigger throttling rules • emulation of front-end buffers • status of subdetector partitions • It generates fast commands (BCRes, L1Reset and other Bgo commands) to be distributed to the subdetectors by the TTC network. • It generates calibration and test trigger sequences. • It has several counters for monitoring purposes, including dead-time counters.

  9. TCS block diagram

  10. Monitoring and dead-time counters on TCS chip • Counters in each of the 8 DAQ partitions: • Nr. of beam crossings (BC) where L1A was inhibited (dead-time counter for all BC). • Nr. of active (according to LHC BC structure) BC where L1A was inhibited (dead-time counter for active BC). • Nr. of BC where L1A was inhibited and L1A is true (lost triggers). • Nr. of distributed physics triggers (physics L1A with dead-time). • Orbit nr. (32-bit).

  11. Monitoring and dead-time counters on TCS chip • Counters existing only DAQ partition 0 (DAQ0): • Nr. of active BC where L1A was inhibited by private orbits. • Nr. of active BC where L1A was inhibited by subdetector partitions. • Nr. of active BC where L1A was inhibited by trigger throttling rules. • Nr. of active BC where L1A was inhibited by calibration or test cycles. • Nr. of physics triggers (physics L1A without dead-time). Note that FDL has counters for all Final OR’s and technical triggers. • Nr. of distributed calibration triggers. • Nr. of distributed random (test) triggers. • Nr. of missing BC (no beam). • Event number (total number of distributed L1A for all partitions, for EVM). Note that the requested dead-time counters for normal rate (all DAQ partitions) and throttled rate (only DAQ0 partition) are now available.

  12. 2 LVDS signals on an Ethernet connector are available to gate luminosity counters: LUM1: Running (reset by start/stop) LUM2: Active time for L1A (OR of all dead-times, inverted) L1AOUT

  13. Controller side Luminosity Server Luminosity DB TS client (Web page) XDAQ executive Monitor Collector L1-Trigger Conditions DB Cell (TS) FL1.xml FL2.xml pull pull Cell (#1) Cell (#2) XDAQ executive XDAQ executive Monitor Sensor Monitor Sensor Control Cell #1 (GT/TCS Leaf) Control Cell #2 (Other subsystem Leaf) FL1.xml DataSource DataSource FL1.xml FL2.xml Trigger Supervisor Monitoring and Conditions DB I. Magrans

  14. Summary The FDL, TCS and L1AOUT boards are relevant for luminosity. Counters for measuring rates and dead-times are available on FDL and TCS boards. Counters can be accessed though VME for monitoring purposes. The luminosity monitoring will be integrated in the central monitoring, using the Conditions Database and the Trigger Supervisor.

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