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Actel RTSX-SU FPGA Reliability Summary

Actel RTSX-SU FPGA Reliability Summary. Daniel Elftmann Director Product Engineering. Agenda. RTSX-SU Introduction RTSX-SU Enhancements Libero design Software Programming Software RTSX-SU FIT Rate Calculator RTSX-SU Voltage & Temperature Acceleration RTSX-SU Summary. RTSX-SU (UMC).

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Actel RTSX-SU FPGA Reliability Summary

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  1. Actel RTSX-SU FPGA Reliability Summary Daniel Elftmann Director Product Engineering

  2. Agenda • RTSX-SU Introduction • RTSX-SU Enhancements • Libero design Software • Programming Software • RTSX-SU FIT Rate Calculator • RTSX-SU Voltage & Temperature Acceleration • RTSX-SU Summary

  3. RTSX-SU (UMC) • Introduced 2004 • Uses 0.22 µm process with 0.25 µm design rules at United Microelectronics Corp (UMC), Taiwan • No ICCI power-cycling inrush current • No UMC Antifuse faults on customer boards or systems

  4. RTSX-SU Reliability Summary: Original Programming Algorithm • Summary of data as of May ’06 • Data set below represents original programming algorithm • Actel Enhanced Lot Acceptance (ELA) and experiments, NASA and Aerospace use highly perceptive and stressful designs • No high programming current antifuse faults observed (~48 Billion high programming current antifuse hours) • Three low programming current antifuse faults detected • 2 Single B-Antifuses (Aerospace), 1 Single S-Antifuse (NASA) • Total of 3 Million device-hours accumulated so far

  5. RTSX-SU Reliability Summary: Libero Design Enhancements • Libero1 Design software enhancements were developed to further improve reliability • S-Antifuse Loading (SAL) – Designer 6.2-SP1, Aug ‘05 • Reduces current stress on S-Antifuses • B-Antifuse Reduction (BAR) – Designer 7.0, Dec ‘05 • Reduces occurrence of single B-Antifuses • Single B-Antifuse Elimination (SBE) – Designer 7.2, Jun’06 (planned) • Eliminates occurrence of single B-Antifuses at significant area and timing penalty • K-Antifuse Buffer Insertion (KBI) – Designer 6.2-SP1, Aug ‘05 • Adds buffers to reduce possibility of clock skew affecting functionality • Actel recommends using the latest Libero1 Design software • Incorporates all enhancements listed above 1 Libero is the integrated design environment software that Designer is a part of.

  6. Single B-Antifuse Elimination(SBE) • Eliminate occurrence of all single B-Antifuse cases • May decrease performance, routability and utilization • Enabled via a definition variable in Designer software • Contact Technical Support or Rich Katz for the definition variable name • Variable is persistent in the Designer database (only needs to be set once) • Warning will be issued that the single B-Antifuse elimination feature is in effect • SBE support for RTSX-SU only (not for SX-A, eX, AX, or RTAX-S) • Testing on designs in the RTSX-SU Tracked design database • 3 of the 69 designs failed to compile due to fan-out violations • 12 out of remaining 66 exceeded area available in selected device • Average C-Cell area increase of 12% • 6 of the remaining 54 designs failed to route • These issues may all be solvable by the FPGA Designer, but will take additional effort

  7. RTSX-SU Reliability Summary: UMA programming algorithm • Enhancements were developed to further advance reliability: • UMC Modified Algorithm (UMA) – Sculptor 3.90/4.53, July ‘05 • Results in more robust programming of low programming current antifuses • NASA and Aerospace use highly perceptive and stressful designs • No high programming current antifuse faults observed • One low programming current K-Antifuse fault detected • K-Antifuses are used to connect routed clock networks to R-cells • Actel recommends against the use of the routed clock for critical clock networks • K-Antifuse Buffer Insertion (KBI) implemented in Designer 6.2-SP1, Aug ’05 • Adds buffers to reduce possibility of clock skew affecting functionality • Total of 1 Million device-hours accumulated so far with UMA

  8. RTSX-SU Design Specific FIT Rate Calculator User Inputs • User inputs • Antifuse count breakdown for specific design of interest • Length of mission in years • Screen time prior to launch of FPGA (restricted to 0, 250, 500 or 1000 hours to obtain information on confidence intervals) • Desired level of perceptivity • High Perceptivity • Assumes any antifuse that has a timing delay increase that is greater than 2 ns is a failure • Medium Perceptivity • Assumes any antifuse that has a timing delay increase that is greater than or equal to 10 ns is a failure • Low Perceptivity • Assumes any antifuse that has a timing delay increase that is greater than or equal to 70 ns is a failure

  9. RTSX-SU Design Specific FIT Rate Calculator Assumptions • Calculator assumptions • Does not account for either Voltage or Temperature acceleration • Subsequent charts will show a 5X acceleration for each 0.25 V above nominal operation of VCCA • Analysis of temperature acceleration yields an effective activation energy of 0.2 eV, which translates to a 3.5X factor from 125 ºC to 55 ºC • Using standard software, does not include SAL, UMA or BAR enhancements • Includes failure rate assumption for high programming current antifuses • No high programming current antifuse faults observed in 12 Million equivalent ’32 class device hours (48 Billion high programming current antifuse hours) • If a single antifuse fails in an FPGA, then the FPGA fails

  10. RTSX-SU Design Specific FIT Rate Calculator (v2.3)

  11. RTSX-SU Average Design FIT Rate Calculation (v2.3) • For a average Customer Design: (850 sensitive antifuses and 14,100 non-sensitive antifuses in design) • 10 year mission, 250 hours of Burn in • High perceptivity design (<10 ns) • Medium perceptivity design (>10 ns but <= 70 ns) • Calculator can be obtained from Actel on request

  12. RTSX-SU Tracked Design Database FIT Rates • Fit Rate for 71 customer provided designs represented in graph above • 10 year mission & 250 hours of Burn-in was used for FIT rate calculations in the analysis above • Tpd in above legend represents the perceptivity to propagation delay delta increase

  13. Voltage AccelerationStress and Acceleration of Programmed Antifuse • Programmed antifuses are stressed and accelerated by increasing the switching current (IPEAK) • Current is the charging and discharging AC current from logic change • Increasing the core voltage (VCCA) increases the IPEAK stress • Spice simulations were run to determine IPEAK stress through antifuses versus VCCA and Junction Temperature • Actel’s calculation of temperature acceleration of effective Ea=0.2 eV is equivalent to a factor of 3.5x from 125 ºC to 55 ºC

  14. Voltage Acceleration Experiments Programming: Standard AlgorithmDesign: High Single S-Antifuse Stress (HiSS) running @ 24 MHzDevice: A54SX72A-PQ208 UMC • All faults were identified to be Single S-Antifuse

  15. Voltage Acceleration Data *This is a highly sensitive design which over-samples Single S-Antifuses by 10X relative to average space design, and is sensitive to 1 ns delay changes (5X more sensitive than average space design) - hence this design is ~50X more sensitive than an average design

  16. Summary • The Aerospace Corporation Industry Tiger Team conducted the final Aerospace Industry Tiger Team meeting on February 15th 2006 • Aerospace Corporation statement : “UMC RTSX-SU is a useable part, it is a good part, and the data shows that it is reliable”

  17. Flight Heritage – RTSX-SU • Many more programs preparing to fly RTSX-SU • GPM, GLAST, SDO, DAWN, OSTM, AMT, Phoenix, ST-7, Kepler, IGS3, . . . Mars Reconnaissance OrbiterLaunched August 12, 2005 GPS 2R-M1Launched Sept 26, 2005 Actel RTSX-SU On Board Actel RTSX-SU On Board Venus ExpressLaunched Nov 9, 2005 Galileo GIOVE-ALaunched Dec 28, 2005 New HorizonsLaunched Jan 19, 2006 Actel RTSX-SU On Board Actel RTSX-SU On Board Actel RTSX-SU On Board

  18. Reference Section

  19. Enhancement #1RTSX-SU Programming Algorithm • UMC Modified Algorithm (UMA) • UMA provides low programming current antifuses longer soaking pulses, in order to ensure no weak links • Includes S, B, I and K antifuses • UMA was released in Silicon Sculptor II Software • Version 3.90 (DOS) / 4.53 (Windows) • Available since July 2005 • UMA uses the new AFM format • Introduced in Designer 6.1-SP1 • Available since March 2005

  20. Enhancement #2S-Antifuse Loading (SAL) • S-Antifuse Loading (SAL) • Adds capacitive loading by connecting a freeway track • Reduces IPEAK in single S-antifuse nets by a minimum of 33% • No measurable increase in routing delay of single S-antifuse nets • Requires design re-layout • Placement will not change, only routing capacitance is added • Timing changes are minimal (<1ns) • Timing analysis encouraged • AFM checksum changes • SAL Availability • Designer / Libero version 6.2-SP1 • Available since August, 2005 Logic Module Logic Module Single S-Antifuse Net Freeway track adds capacitive loading

  21. DB-Inverter/B-Antifuse Description • In the RTSX-SU architecture each C-Cell has a dedicated local inverter, the DB-Inverter • DB-Inverter description • The DB-Inverter has an input or I-Antifuse to enable connection to the output of a C-Cell, R-Cell, or Input Buffer • The DB-Inverter has a dedicated output routing track with a total of six B-Antifuses on it • Any of the logically unique inputs to the C-Cell may be connected to the output of the DB-Inverter by programming a B-Antifuse • When the B-Antifuse is programmed for a C-Cell input then no I-Antifuse will be programmed for that input • When a DB-Inverter drives only one programmed B-Antifuse, then it is classified as a Single B-Antifuse

  22. B-Antifuse utilization dependency on the Macro Function Library • 4,258 unique macro functions exist in the RTSX-SU library • 16,879 different configurations • 3,903 of the macro functions utilize B-Antifuses • None of the 3,903 have a don’t care input available for additional loading– like SAL • 3,045 macros functions have Single B-Antifuse configurations • 2,580 have no single C-Cell option • Would require 2 C-Cells to eliminate and changes to customer netlist– This option will be available in Q3’06 • 355 can be implemented with a No B-Antifuse configuration(s) • 110 have options with a Multiple B-Antifuse configuration(s) • Designer 7.0 B-Antifuse Reduction Change • Removes Single B-Antifuse configurations for the 355 macro functions that have a configuration option with no B-Antifuse • Removes Single B-Antifuse configurations for the 110 macro functions that have a configuration option with multiple B-Antifuses • When evaluated on the tracked customer Designs at Actel the average reduction in Single B-Antifuses was 40%

  23. RTSX-SU/A54SX-AC-Cell K-Antifuse Connections

  24. RTSX-SU/A54SX-AR-Cell K-Antifuse Connections

  25. Definition of CriticalK-Antifuses

  26. How to get Design Statistics • Actel is providing compiled binary Perl scripts to extract various design utilization statistics that will amongst other things provide customer with the number of Single S-Antifuses, Single B-Antifuses, Critical K-Antifuses in their design • Compiled binary Perl scripts currently available for Windows PC, Solaris, or Linux operating systems • Scripts require that the Designer software be installed on the machine running the compiled binary Perl script • Path to Designer software must be in the environmental variables • Customer Applications Engineers are trained and ready to support or run the scripts for Actel customers on their ADB files • Email: tech@actel.com Phone (North America): 800-262-1060 Phone (International): +1 650-318-4460

  27. Antifuse Statistics for FIT CalcScript Output • ******************************************************************************** • K-Antifuse port connections report • ******************************************************************************** • Chip Wide Total Number of K-antifuse ports found = 490 K-Antifuses = 490 • CLK = 458 • CLR = 0 • PRE = 0 • S00 = 1 • S01 = 10 • S10 = 0 • S11 = 17 • S0 = 0 • S1 = 0 • A = 4 • B = 0 • C = 0 • D = 0 • E = 0 • G = 0 • Routed Clock number of register pairs with Q->D = 147 • Routed Clock number of register pairs with Q->E = 0 Critical K-Antifuses for FIT calculation will be the sum of Q->D + Q->E However, this result cannot exceed the total of K-Antifuses used to make CLK (RC) connections

  28. Antifuse Statistics for FITCalculator Script Output ******************************************************************************** S-Antifuse Only report ******************************************************************************** Total Nets that are not S-Antifuse only type nets = 2274 Total Nets that use only 1 S-Antifuse = 230 Total Nets that use only 2 S-Antifuses = 113 Total Nets that use only 3 S-Antifuses = 31 Total Nets that use only 4 S-Antifuses = 10 Total Nets that use only 5 S-Antifuses = 3 Total Nets that use only 6 S-Antifuses = 1 Total Nets that use only 7 S-Antifuses = 1 ******************************************************************************** Active Repeater nets = 0 ******************************************************************************** DB Inverter Summary ******************************************************************************** Direct Connects = 451 Total DB Nets = 611 Total Nets that use only 1 B-Antifuse = 537 Total Nets that use only 2 B-Antifuses = 69 Total Nets that use only 3 B-Antifuses = 5 Single S-Antifuses Single B-Antifuses

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