StaticRoute : A novel router for the dynamic partial reconfiguration of FPGAs

1. StaticRoute: A novelrouter forthe dynamicpartialreconfiguration of FPGAs Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt

2. Overview • Dynamic reconfiguration of FPGAs: • Modular dynamic reconfiguration (MDR) • Dynamic circuit specialization (DCS) • Novel tool flow • Experiments and results • Conclusions

3. FPGA FF LUT 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1

4. Conventional FPGA tool flow HDLdesign SYNTHESIS MAP PLACE ROUTE Configuration Input: textual description of functionality

5. Textual description: HDLdesign in0 entity multiplexer is port( sel : in std_logic_vector(1 downto 0); in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; in1 out in2 in3 sel0 sel1

6. Conventional FPGA tool flow HDLdesign SYNTHESIS MAP 100101 011100 001111 PLACE ROUTE Configuration Input: Textual description of functionality Output: FPGA configuration

7. Dynamic reconfiguration of FPGAs M3 M3 M1 M1 M2 M2 • Advantages: • Smaller area • Lower power usage • Disadvantage: • Reconfiguration time • Goal: area reduction with reduced reconfiguration time

8. Dynamic reconfiguration of FPGAs M3 M3 M1 M1 M2 M2 • 2 tool flows: • Modular Dynamic Reconfiguration (MDR) • Dynamic Circuit Specialization (DCS)

9. Modular Dynamic Reconfiguration (MDR) Mode 1 Mode 2 SYNTHESIS SYNTHESIS MAP MAP PLACE PLACE ROUTE ROUTE Configuration 1 Configuration 2

10. MDR • Different modes are implemented independently • Complete area is rewritten  Results in long reconfiguration times

11. Dynamic Circuit specialization • Design with parameters: input signals that only change once a while • Implement dependency on parameters using dynamic reconfiguration

12. Dynamic circuit specialization Param. HDL SYNTHESIS TMAP TPLACE TROUTE Param. Conf. Input: annotatedtextual description of functionality

13. Parameterised HDL design entity multiplexer is port( --BEGIN PARAM sel : in std_logic_vector(1 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; in0 in1 out in2 in3 sel0 sel1

14. Dynamic circuit specialization Param. HDL SYNTHESIS TMAP TPLACE TROUTE Param. Conf. Input: Annotatedtextual description of functionality

15. Dynamic circuit specialization Param. HDL SYNTHESIS TMAP 1A0101 0111B0 0C1111 A= sel0AND sel1 B= sel1 C= sel0OR sel1 TPLACE TROUTE Param. Conf. Input: Annotatedtextual description of functionality Output: Parameterised configuration

16. TRoute

17. Dynamic Circuit Specialization • Reduced reconfiguration time • Takes as input 1 parameterised design • How to implement several modes with DCS?

18. Goal of our research • Develop tool flow for dynamic reconfiguration of multi-mode circuits • Reduce reconfiguration time • Combined routing of different modes using TRoute:  Increase correlation between configurations of the different modes

19. Novel tool flow Mode 1 Mode 2 SYNTHESIS SYNTHESIS MAP MAP PLACE PLACE ROUTE ROUTE Merge Configuration 1 Configuration 2 TROUTE Param. Conf.

20. Experiments • Regular expression matching hardwareand general MCNC benchmarks • Circuits of 200-400 LBs • 2 to 5 modes considered • Comparison of MDR and DCS (this work) • Metrics: • Reconfiguration time • Wire length (of each mode separately)

21. Results – Reconfiguration time • Speed-up of routing reconfiguration time • Speed-up of total reconfiguration time

22. Results – Reconfiguration time routing (MDR)

23. Results – Total reconfiguration time (MDR)

24. Results – Wire length

25. Conclusions • Using novel tool flow that uses TRoute: • Total reconfiguration speed-up of 3X to 5X • Increase in wire length between 10 to 25 percent

26. A noveltool flow forincreased routing configurationsimilarity in multi-mode circuits Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt