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Inverter Domino Chain

Domino Ring Sampler (DRS). Speed Control (V) 2 – 4 GHz. Rotating sampling wave. Inverter Domino Chain. Synchr. Domino Wave. Domino Wave. 1024 cells. Impulse. Analog input. Analog output. Clock 40MHz. SROUT. Readout Shift Register. SRCLK. SRRES. SRIN. SRCLK. DRS2 Mezzanine.

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Inverter Domino Chain

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  1. Domino Ring Sampler (DRS) Speed Control (V) 2 – 4 GHz Rotating sampling wave Inverter Domino Chain Synchr Domino Wave Domino Wave 1024 cells Impulse Analog input Analog output Clock 40MHz SROUT Readout Shift Register SRCLK SRRES SRIN SRCLK

  2. DRS2 Mezzanine PULSAR CONNECTOR SINGLE ENDED DIFFERENTIAL DRS2 Input Stage High BW Differential Amplifier TRIGGER SERIAL P.I. ADC/DAC PLL CLK POWER SUPPLY T SENSOR 40 MHz ADC (AD9235 12 – bit) RECEIVER BOARD CONNECTOR 2 PLLs (in BOTTOM side)

  3. TRIGGER DISTRIBUTION BOARD TRIGGER DISTRIBUTION BOARD CLOCK DISTRIBUTION BOARD CLOCK DISTRIBUTION BOARD ABORT BUSY L 1 I N L 1 I N L 1 I N L 1 I N L 1 I N L 1 I N L 1 I N L 1 I N DIGITAL DATA DIGITAL DATA DIGITAL DATA M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z CPUVME L 1 O U T L 1 O U T L 1 O U T L 1 O U T L 1 O U T L 1 O U T L 1 O U T L 1 O U T 1 M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z D I G I TAL PULSAR PULSAR ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG PULSAR PULSAR PULSAR PULSAR PULSAR PULSAR ABORTBUSY BUSY 2 M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z S V T I N S V T I N S V T I N S V T I N S V T I N S V T I N S V T I N S V T I N 24 51 S V T O U T S V T O U T S V T O U T S V T O U T S V T O U T S V T O U T S V T O U T S V T O U T M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z M E Z Z 52 25 From TRIGGER SYSTEM 7 1 5 12 6 0 VME CRATE 1 VME CRATE 2 0 1 10 11 25 26 51 52 RECEIVER BOARDS: 1039 CAMERA SIGNALS

  4. 2 DRS2 cards RAM RAM ANALOG DATAIO FPGA CONTROL FPGA CONTROL FPGA HOLA FILAR SVT IN FILAR HOLA VME INTERFACE HOLA FILAR DRS CONTROL DRS CONTROL PC PC DATA DATA Send ADCx2 ADCx2 DATA BLOCK DATA BLOCK 24 Sstart CLK40MHz CLK40MHz CLK40MHz DATA DATA DATA 32 VME SIGNALS ADCx2 ADCx2 24 HOLD SVT IN CABLE CH_WORD SE_WORD EE_WORD TRIG CELL-TRIG NUMB Sstart TRIGGER Send VME SIGNALS DATAEN SRAM CONTROLLER CLK40MHz SUPER SEQUENCER SUPER SEQUENCER DATA CLK40MHz ADDR WREN CEN UDATA UWE LFF BUSY 17 32 ST_RD ST_DRS SRCKEN ADCCKEN CH_ADD 32 4 SRAM SRAM CTRL SIGNALS CLK40MHz UDATA UDATA UWE UWE LFF LFF Mezzanines Hardware Mezzanines Hardware 32 32 SRRES SRCLK P3 P3 SRIN

  5. PULSer And Recorder DIGITAL PULSAR DRS Mezzanine Trigger Number, Digital Data Trigger Cell ANALOG PULSAR Read-Out System, Data Format Trigger Cell and Trigger Number propagation via SVT cable Region-of-Interest: 100 samples DRS Mezzanine fc = 2.5 GHz 1 Domino cell = 0.4 ns RoI Read-out system of 1200 channels: 1 Digital + 15 Analog PULSARs 1024 samples/ch ~2,4 GBytes/s @ 1 kHz max 4 h Acquisition Time ~34 TBytes With Region of Interest (RoI): 100 samples/ch 240 MBytes/s@ 1 kHz max 4 h Acquisition Time~3,4 TBytes Trigger Latency 250 cells wide 100 cells wide

  6. Data Acquisition System Daisy- chained distribution of trigger number and trigger cell Consistence Tests and verify

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