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Ultra low power PLL design and noise analysis

Ultra low power PLL design and noise analysis. EE241 Prof. Borivoje Nikolic Peter Chen, Mingcui Zhou. Choice of PLL : type II 3rd order . Power consumption < 1mW Frequency of operation: Reference from power link: 1MHz Data carrier: 32MHz

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Ultra low power PLL design and noise analysis

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  1. Ultra low power PLL design and noise analysis EE241 Prof. Borivoje Nikolic Peter Chen, Mingcui Zhou

  2. Choice of PLL : type II 3rd order • Power consumption < 1mW • Frequency of operation: Reference from power link: 1MHz Data carrier: 32MHz • We operate the VCO at twice the data carrier frequency (64Mhz) to get good 50% duty cycle after dividing by 2. • Parts: + PFD, ChargePump + 2nd order passive filter + voltage controlled 3-stage ring-oscillator + 1/64 frequency divider

  3. System block diagram Kp=18uA/2pi Kv=200MHz/Volts N=64 Bode plot

  4. Tracking time • Using Matlab determine the optimum loop filter parameter for enough phase margin and settling time. • Loop filter choice: Cp=2uF, R=10k C2=42pF damping= 0.66 • Settling =60us ~60 times reference frequency. Impulse response and step response of designed system

  5. Block design: VCO

  6. Frequency Divider

  7. Phase Frequency Detector and Charge Pump

  8. Simulation Result Simulation of Vctrl using Best’s software Transients of PLL Red: output of divider Blue: input reference System performance: Power: 280.3uW Cycle to cycle jitter:1.91ns Lock-in time: 65us Simulation of Vctrl using Hspice

  9. Powerdissipation • VCO power=225.7uW • @ 64MHz supply=1.8v • PFD and charge pump power=53.7uW the main power drain is bias branch for charge pump • Divider power=4.176uW @ 64MHz • Total power=280.3uW • When VCO operate at fmax=140MHz, the total power of the PLL is still under 1mW. Specs achieved. blue: VCO red: divider N=64 Green: charge pump. current flow from voltage supply for each block)

  10. Noise in PLL: low pass, high pass Where G(s)=KH(s)/(sN) All the noise sources share the same loop gain, however with different open loop gain. Since the open loop gain of the VCO doesn’t include filter H(s), it’s characteristic is very different from other noise source, and is termed as high pass noise in the PLL.

  11. Noise of PLL: synchronous/Accumulating jitter The bode plot describes the system characteristic in terms of frequency. Transfer function of each noise source is plotted using parameter of the design System closed loop gain Closed loop of VCO noise source to output Closed loop of PFD noise source to output

  12. Noise generation in PFD/CP Noise mechanism in PFD • Current mismatch in charge pump pull down, pull up network • Leakage current • Reset delay • Up/Down Signal arriving time difference. • Decreasing the transistor size and bias current lower power dissipation at the expense of mismatch Reset delay causes fluctuation of Vctrl

  13. VCO noise The main noise contributor in a PLL i) Transistor thermal noise ii) Supply/substrate noise: measured supply gain to output frequency: Ks=0.3MHz/v 57dB difference compared to Kv Using Spectre calculating steady state phase noise of oscillator (Without supply/substrate noise) • 12.8dBc @ 2.5MHz • 1/f roll-off

  14. Don’t even think about all-digital PLL (ADPLL) if you want very low-power operation A novel low-power and low noise VCO design would be very attractive (e.g. MEMS?) Conclusions

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