1 / 18

RCU Status

RCU Status. HiB, UiB, UiO. RCU design RCU prototypes RCU-SIU-RORC integration RCU system for TPC test 2002. 1. RCU design – system architecture. RCU design – control flow. State machines. TTCrx. SIU controller. FEE bus controller. DDL command decoder. FEE SC. RCU

michi
Télécharger la présentation

RCU Status

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. RCU Status HiB, UiB, UiO • RCU design • RCU prototypes • RCU-SIU-RORC integration • RCU system for TPC test 2002

  2. 1. RCU design –system architecture

  3. RCU design –control flow • State machines TTCrx SIU controller FEE bus controller DDL command decoder FEE SC RCU resource & priority manager Huffman encoder Slow control Watch dog: health agent Debugger PCI core

  4. RCU design - data flow • Shared memory modules TTC controller TTCrx registers FEE bus controller Event memory SIU controller fifo FEE bus controller Event fragment pointer list SIU Huffman encoder FEE bus controller Configuration memory Slow control

  5. 2. RCU prototypes • Prototype I • Commercial OEM-PCI board • FEE-board test (ALTRO + FEE bus) • SIU integration • Qtr 3, 2001 – Qtr 2, 2002 • Prototype II • Custom design • All functional blocks • PCB: Qtr 2, 2002 • Implementation of basic functionality (FEE-board -> SIU): Qtr 2, 2002 • Implementation of essential functionalty: Qtr 4, 2002 • Prototype III • SRAM FPGA -> masked version or Antifuse FPGA (if needed) • RCU production • Qtr 2, 2003

  6. RCU prototype I • Commercial OEM-PCI board • ALTERA FPGA APEX EP20K400 • SRAM 4 x 32k x 16bits • PMC I/O connectors (178 pins) • Buffered I/O (72 pins)

  7. RCU prototype I • Implementation of basic test functionality • FEE-board test (ALTRO + FEE bus) • SIU integration FEE boards trigger FEE-bus daughter board PMC PCI bus FPGA APEX20k400 PCI core I/O SIU card internal SRAM 4 x 32k x 16 FLASH EEPROM onboard SRAM

  8. RCU prototype II • Implementation of essential functionality • Custom design • All functional blocks SC TTC FEE-bus PCI bus SIU-CMC interface PCI core FPGA SIU internal SRAM > 2 MB FLASH EEPROM Memory D32

  9. RCU prototype II - schematics

  10. Programming model PCI-tools PC LINUX RH7.1 (2.4.2) RCU-API • Development version – status December 2001 device driver PCI core mailbox memory PLDA board FEE bus controller SIU controller ALTRO emulator FEE bus SIU ALTRO emulator DDL

  11. 3. SIU-RORC integration • SIU-controller functions implemented: • Read RCU status word • Write register to RCU • Read events from RCU • Not yet implemented: • Write block to RCU • Read block from RCU RCU prototype I LINUX/NT PLDA/PCI-tools RCU-API devicer driver SIU FPGA interface SIU controller PCI core SIU SRAM PCI bus DDL pRORC LINUX DDL/PCI-tools pRORC-API device driver DIU Glue logic PCI bridge interface DIU PCI bus

  12. SIU-RORC integration • System setup, Bergen, Nov./Dec. 2001

  13. SIU-RORC integration PC1: write memory block to FPGA internal SRAM PC1 memory block • Result data control PC2: allocate bigphys area, init link + pRORC RCU internal SRAM SIU controller: wait for READY-TO-RECEIVE PC2: send DDL-FEE command READY-TO-RECEIVE SIU SIU controller: strobe data into SIU DDL DIU pRORC: copy data into bigphys area via DMA PC2 ”bigphys” memory area =

  14. 4. RCU system for TPC test 2002 • RCU requirements • Readout of 4 FEE-bus branches • 2 RCU prototypes II • Fallback solution: • 4 RCU prototypes I (3 boards are available) • Basic RCU functionalty • Develop logics for readout of all FEE cards on FEE-bus • Include external SRAM • Develop Manager SM for controlling data transfer from FEE-bus to SIU • Include simple trigger and event-ID • Interface to DAQ • DATE • DAQ via DDL • 2 pRORC (including SIU + DIU) • Integrate pRORC into DATE (DAQ-group) • Fallback solution: • DAQ via RCU-PCI

  15. RCU system for TPC test 2002 FEE-boards RCU prototype II/I Trigger FEE-bus LINUX RH7.x DATE PLDA/PCI-tools RCU-API devicer driver SIU FPGA interface FEE-bus controller SIU controller Manager PCI core SIU SRAM FLASH ext. SRAM PCI bus DDL pRORC LINUX RH7.x DATE DDL/PCI-tools pRORC-API device driver DIU Glue logic PCI bridge interface DIU PCI bus

  16. Programming model DATE FEE configurator PC LINUX RH7.1 (2.4.2) PCI-tools RCU-API • TPC test version – summer 2002 device driver PCI core mailbox memory Prototype II (Prototype I) SIU controller RCU resource & priority manager FEE bus controller FEE bus SIU FEE boards DDL

  17. Open questions (1) • Radiation induced corruption of SRAM • Configuration SRAM bit toggle rate > O(1/hour) • Replace SRAM based FPGAs with • masked versions (expensive) • or Antifuse FPGAs (additional prototyping – 6 months?) • Configuration SRAM bit toggle rate < O(1/hour) • External watch dog circuit • periodical check of configuration SRAM • reload FPGA configuration • STAR experience • TPC and FTPC FEE: SRAM-based FPGAs • Not a single incident observed in approx. 100 days of operation • Estimate for ALICE • SRAM bit toggle rate < O(1/day)??? -> Quantitative study needed - wait for SIU results

  18. Open questions (2) • Firmware • Interface to many different subdetectors (SC, Trigger, DDL, DAQ, FEE-bus) • Fully debugged hardware/firmware/software not always available -> develop emulators - needs experts and time • Software • High level test software • DATE applications • Online monitoring for TPC test -> who?

More Related