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Flip-Flop Circuits CPEG 324

Flip-Flop Circuits CPEG 324. V IN. V OUT. Inverter. Bistable element. HIGH. LOW. LOW. HIGH. LOW. HIGH. HIGH. LOW. Analog analysis. Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V. 2.51 V. 2.5 V. 4.8 V. 5.0 V. 2.5 V. 2.0 V. 0.0 V. 2.5 V.

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Flip-Flop Circuits CPEG 324

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  1. Flip-Flop CircuitsCPEG 324

  2. VIN VOUT Inverter

  3. Bistable element HIGH LOW LOW HIGH LOW HIGH HIGH LOW

  4. Analog analysis • Assume pure CMOS thresholds, 5V rail • Theoretical threshold center is 2.5 V 2.51 V 2.5 V 4.8 V 5.0 V 2.5 V 2.0 V 0.0 V 2.5 V 2.0 V 0.0 V 2.5 V 4.8 V 5.0 V

  5. Metastability • Metastability is inherent in any bistable circuit • Two stable points, one metastable point

  6. Another look at metastability

  7. Why all the harping on metastability? • All real systems are subject to it • Problems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times. • Especially severe in high-speed systems • since clock periods are so short, “metastability resolution time” can be longer than one clock period. • Many digital designers, products, and companies have been burned by this phenomenon.

  8. Pass Transistor VIN VOUT C When C=1, then VIN = VOUT or Electrical Short: VOUT VIN When C=0, then Electrical Open between VIN and VOUT: VOUT VIN

  9. D C X D Latch • Feedback inverter (X) is “weak” • When C=1, D will overpower X and force Q=D.

  10. D-latch operation latch acts like a wire while its control is active flip-flop (later) grabs data when control changes

  11. D-latch timing parameters • Propagation delay (from C or D) • Setup time (D before C edge) • Hold time (D after C edge)

  12. QM Master Slave D-Latch D-Latch D Flip-Flop based on Bistable Element

  13. D Flip-Flop Operation latch acts like a trigger at the rising edge of CLK it grabs data (D) and stores it (Q).

  14. D flip-flop timing parameters • Propagation delay (from CLK) • Setup time (D before CLK) • Hold time (D after CLK)

  15. Worst-case Military Conditions, VCCA=2.3, VCCI=3.0V, TJ=125C -1 Speed Grade Min Max Units tRCO Sequential Clock-to-Q 1.0 ns tCLR Asynchronous Clear-to-Q 0.9 ns tPRESET Asynchronous Preset-to-Q 1.0 ns tSUD Flip-Flop Data Input Set-Up 0.6 ns tHD Flip-Flop Data Input Hold 0.0 ns tWASYN Asynchronous Pulse Width 1.8 ns Example: RT54SXS Flip-Flop

  16. Hand-Drawn Metastability Example

  17. Metastability - Introduction • Can occur if the setup, hold time, or clock pulse width of a flip-flop is not met. • A problem for asynchronous systems or events. • Can be a problem in synchronous systems. • Three possible symptoms: • Increased CLK -> Q delay. • Output a non-logic level • Output switching and then returning to its original state. • Theoretically, the amount of time a device stays in the metastable state may be infinite. • Many designers are not aware of metastability.

  18. Metastability • In practical circuits, there is sufficient noise to move the device output of the metastable state and into one of the two legal ones. This time can not be bound. It is statistical. • Factors that affect a flip-flop's metastable "performance" include the circuit design and the process the device is fabricated on. • The resolution time is not linear with increased circuit time and the MTBF is an exponential function of the available slack time.

  19. CLK D Q Metastable Metastable State:Possible Output from a Flip-flop

  20. CLK Q Q Q Correct Output Metastable State:Possible Outputs from a Flip-flop Correct Output

  21. Metastability

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