Development of a System-On-Chip Extensible Network Processor and debugging using Identify

1. Development of a System-On-Chip Extensible Network Processor and debugging using Identify John W. Lockwood and Chris Zuver Applied Research Laboratory : Reconfigurable Network Group http://www.arl.wustl.edu/projects/fpx/reconfig.htm lockwood@arl.wustl.edu cz2@arl.wustl.edu

2. FPX Hardware Platform

3. FPX Hardware in WUGS-20 Switch

4. FPX Hardware in GVS-1000 Chassis

5. System-On-Chip Firewall

6. Content Matching Module regex_app (given) dataen_out_appl d_out_appl sof_out_appl eof_out_appl sod_out_appl tca_out_appl clk reset_l enable_l dataen_appl_in d_appl_in sof_appl_in eof_appl_in sod_appl_in tca_appl_in Matched ready_l 32 32 From Protocol Wrappers To existing MP1 circuit To extended Bits of CAM 8 wrapper_module.vhd

7. Packet matching w/ Content Addressable Memory • Sample Packet: • Source Address = 128.252.5.5 (dotted.decimal) • Destination Address = 141.142.2.2 (dotted.decimal) • Source Port = 4096 (decimal) • Destination Port = 80 (decimal) • Protocol = TCP (6) • Payload = “Consolidate your loans. CALL NOW” • Payload Lists = { General SPAM (0), Save Money SPAM (1) } • Content Vector = “00000011” (binary) = x”03” (hex) 111 104 103 71 39 7 40 8 0 72 Dest IP (hex) = 8D8E0202 Con- tent = 03 Src IP (hex) = 80FC0505 SrcPort = 1000 Dest Port = 0050 Proto = 06 All values shown In hex

8. Sample Filter • Source Address = 128.252.0.0 / 16 • Destination Address = 141.142.0.0 / 16 • Source Port = Don’t Care • Destination Port = 80 • Protocol = TCP (6) • Payload includes general SPAM (List 0) Con- ten t= 01 Src IP value = 80FC0000 Dest IP (hex) = 8D8E0000 SrcPort = 0000 Dest Port = 50 Proto = 06 Value Mask: 1=care 0=don’t care Con- ten t= 01 Src IP (hex) = FFFF0000 Dest IP (hex) = FFFF0000 SrcPort = 0000 Dest Port = FFFF Proto = FF 103 71 39 7 40 8 0 72 Dest IP (hex) = 8D8E0202 Con- tent= = 03 Src IP (hex) = 80FC0505 SrcPort = 1000 Dest Port = 0050 Proto = 06 IP Packet DROP the packet : It matches the filter

9. Packet Classifier with FlowID 16 bits 112 bits Flow ID [1] CAM MASK [1] CAM VALUE [1] Flow ID [2] CAM MASK [2] CAM VALUE [2] 16 bits - - CAM Table - - Flow ID Flow ID [3] CAM MASK [3] CAM VALUE [3] . . . Resulting Flow Identifier . . . . . . Flow ID [N] CAM MASK [N] CAM VALUE [N] Bits in IP Header Flow List Priority Encoder Source Port Protocol Payload Match Bits Mask Matchers Dest. Port Source Address Destination Address Value Comparators

10. Other Modules Implemented IPv4 CAM Filter 104 Bit header matching Fast IP Lookup (FIPL) Longest Prefix Match MAE-West at 10M pkts/second Packet Content Scanner Reg. Expression Search Data Queueing Per-flow queue in SDRAM IPv6 Tunneling Module Tunnels IPv6 over IPv4 Statistics Module Event counter Traffic Generator Per-flow mixing Video Recoder Motion JPEG Embedded Processor KCPSM

11. Use of Identify in the FPX Design Flow • Identify is natural additional to the current design flow • Adds two new steps • Instrument • Debug

12. Two Part Solution • Instrumenter • Assigns signals to monitor/trigger • Modifies existing VHDL • Does not change original vhdl (create copies) • Streamlines synthesis • Debugger • Communications to hardware via JTAG • Uses trigger setup • Includes waveform viewer • Creates VHDL simulation model

13. Instrumenter : Step 1 • Import Synplicity Project File • File >> Import Synplicty Project ….

15. Instrumenter : Step 2 • Choose Signals to Monitor • Right-click glasses symbol near signal to • Sample and Trigger • Sample Only • Trigger Only

16. Instrumenter : Step 3 • Set Options • Click Edit IICE Options

17. Device Family JTAG port Builtin – Using RJ-45 Port on FPX Syn – Adds four JTAG I/O to toplevel (map rad_test) Name of Clock in VHDL Physical Resource Usage

18. BufferType Deviceram – Block RAM Logic – Flip-Flops Number of Sample (Trade-Off: Resources)

19. Triggering Options Self-Explanatory

20. Instrumenter : Step 4 • INSTRUMENT DESIGN • Click “Save and Instrument Current Project”

21. Synthesis • Open Synplicty • RUN >> Run TCL Script… • Locate Synplicity.tcl in syn_projectname folder

22. Synthesis VHDL Files Containing Instrumented Design Synplicity Synthesis Directory (.edf file here after running Synthesis) TCL Script for Importing to Synplicity Note: New Directory created by Instrumenter in Folder where imported Synplicity Project is located

23. Continue Design Flow • Add .edf file to build directory • Generate Bitfile like usual • Load Bitfile to FPX using NCHARGE • Make sure JTAG cable is unplugged • Connect JTAG Cable to FPX and PC running IDENTIFY (Parrallel JTAG) • Open IDENTIFY Debugger

24. IDENTIFY DEBUGGER • File >> Open Project • Locate the Instrumenter Project File • Should be in same directory as Synplicity Project file

25. IDENTIFY DEBUGGER • Trigger • Locate and set Trigger Event • Right Click Signal

26. IDENTIFY DEBUGGER • Setup Project Options

27. IDENTIFY DEBUGGER Xilinx JTAG Cable

28. IDENTIFY DEBUGGER RUN Waveform STOP Locate Trigger Signals Relative Trigger Event (Trigger Beginning, Middle, End of Sample)

29. IDENTIFY DEBUGGER • Waveform

30. IDENTIFY DEBUGGER • RTL View

31. References • Debugging of an Internet Packet Scheduler Using the Identify Software, by Christopher K. Zuver and John W. Lockwood, The Syndicated, Volume 4, Issue 4, 2004. • An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall, by John W. Lockwood, Christopher Neely, Christopher Zuver, James Moscola, Sarang Dharmapurikar, and David Lim; Field Programmable Logic and Applications (FPL), Lisbon, Portugal, pp. 859-868 (Paper 14B), Sep 1-3, 2003. • Automated Tools to Implement and Test Internet Systems in Reconfigurable Hardware, by John W. Lockwood, Chris Neely, Chris Zuver, Dave Lim; SIGCOMM Computer Communications Review (CCR), vol 33, no 3, July 2003, pp 103-110.