Monolithic Pixel Sensor in SOI Technology - Latest Results

1. Monolithic Pixel Sensor in SOI Technology- Latest Results H. Niemiec, T. Klatka, M. Koziel, W. Kucewicz, S. Kuta, W. Machowski, M. Sapor, M. Szelezniak AGH – University of Science and Technology, Krakow K. Domanski, P. Grabiec, M. Grodner, B. Jaroszewicz, A. Kociubinski, K. Kucharski, J. Marczewski, D. Tomaszewski Institute of Electron Technology, Warszawa M. Caccia University of Insubria, Como Presented by Halina Niemiec

2. Outline • Short introduction to the SOI sensor • Progress of the SOI sensor project since the Amsterdam meeting • Preliminary test of the small area SOI sensors on the high resistive substrates • Tests of the readout scheme • Design of the full size SOI sensor The SOI project is partially supported by the G1RD-CT-2001-000561 AGH-University of Science and Technology & Institute of Electron Technology, Poland

3. Introduction Advantages: The SOI sensor merges the advantages of the monolithic and hybrid detectors • As a monolithic device allows reduction of total sensor thickness and eliminates bump-bonding process • Allows using high resistive detector substrates –good detection efficiency • Gives possibility to use both type of transistors in readout channels – increased flexibility of the design • Tolerance of the readout electronics for SEE benefits from reduction of active silicon thickness The idea: Integration of the pixel detector and readout electronics in the wafer-bonded SOI substrate Detector handle wafer • High resistive • 300 m thick Electronics active layer • Low resistive • 1.5 m thick AGH-University of Science and Technology & Institute of Electron Technology, Poland

4. Progress of the project Concept of the SOI sensor Technological sequence definition Over 100 individual process Limited thermal budged, long lasting high temperature process before pixel creation Front-end conceptual design Readout cell similar to the 3T cell, readout scheme: external CDS, well defined integration time, short dead time Prague workshop Two iteration of the SOI test structure fabrication First lot–standard CMOS devices produced Second lot–cavities for pixel junction created Fabrication and preliminary tests of the prototype readout circuits Commercial AMS 0.8 technology, layout compatible with IET-SOI 3.0 technology Amsterdam workshop Characterization of the prototype readout circuits Validation of the readout scheme, comparison with SOI readout matrices Third iteration of the SOI test structure on high resistive substrates Sensor matrices with pixel junctions created, tests with laser light and radioactive source Today Realization of the complete, full size SOI sensor Next year AGH-University of Science and Technology & Institute of Electron Technology, Poland

5. % % % % Summary of the earlier results for TS-SOI • CMOS technology: • High reliability and low mismatches of the devices • Development of level 2 and 3 model files with dedicated MOSTXX extraction tool • Static and dynamic parameters of the digital standard cells measured for VDD=5V. Max clock freq. up to few MHz. • Pixel cavities • Proofed reliability of the connections to the detectors and metal lines over pixel cavities AGH-University of Science and Technology & Institute of Electron Technology, Poland

6. Preliminary test of small area SOI sensors Readout matrices on SOI test structures: • E14 – 88 readout channels with switches in the form of transmission gates and contacts to the pixel diodes • E15 – 65 matrix of readout channels with switches in the form of transmission gates and test signal input pads • E16 – 88 matrix of readout channels with one-transistor switches and contacts to the pixel diodes • E17 – 55 matrix of readout channels with one-transistor switches and test signal input pads AGH-University of Science and Technology & Institute of Electron Technology, Poland

7. Characterization of readout channels on TS-SOI Matrix with transmission gates Transfer characteristics were measured with external voltage pulse signal, assuming that the charge to voltage conversion ratio for the SOI detector is about 6mV/MIP. • Dynamic range: 0.3 MIP  300 MIP • Output r.m.s. noise:  270 V • Cross-talk between neighbouring channels: < 0.1 % The circuit is optimised for the applications where high particle fluxes are expected AGH-University of Science and Technology & Institute of Electron Technology, Poland

8. Characterization of readout channels on TS-SOI Matrices on TS-SOI vs. prototype front-ends • For prototype front-ends: Output range:1.75 V Input range: 230 MIP Non-linearity (with respect to FS):1% • Matrices on SOI test structures - worse linearity but wider dynamic range as the result of different device characteristics. Improvement of linearity may be possible by the transistor dimension adjustment. Matrix with NMOS switch vs. matrix with transmission gate • For matrix with NMOS switch: Dynamic range: 0.3 MIP  150 MIP Output r.m.s. noise:  300 V Cross-talk between neighbouring channels:< 0.1 % AGH-University of Science and Technology & Institute of Electron Technology, Poland

9. Preliminary test of small area SOI sensors • Matrices with one-transistor switches were chosen for the tests of the complete sensor. • Single cell dimensions for these matrices are 140 x 122 m2. • Matrix dimensions: 1120 m 976 m • Backplane of the detector was biased by metal mesh with rectangular holes to minimize the probability of the light reflection in the laser tests • Leakage currents were estimated • Sensitivity for ionising radiation was preliminary tested with not focused laser light (=850 nm) and Strontium 90 radioactive source Readout channel with integrated detector AGH-University of Science and Technology & Institute of Electron Technology, Poland

10. Estimation of the leakage currents • Indirect method of the leakage current measurements - the output signals corresponding to the integrated leakage current measured for the detector polarization up to the 100V • For the integration time of 500 s and charge to voltage conversion ratio of 6mV/MIP: Ileakage 400 nA/cm2 • Full depletion at about60 V The value of the leakage current determined by the quality of the SOI substrate – similar results obtained for the detector produced on the SOI wafers with etched-down upper Silicon layer (no electronic device produced) AGH-University of Science and Technology & Institute of Electron Technology, Poland

11. Preliminary tests with radioactive source Strontium 90 beta source – recorded events in the detector • Source placed on the top of the detector • Detector polarization: Vdet = 60 V, different integration times • „Steps” on the output waveforms indicate detected particles Tinteg=2 ms Tinteg=1 ms AGH-University of Science and Technology & Institute of Electron Technology, Poland

12. Calibration of the SOI sensor • Radioactive source: Sr90 beta source • Integration time: Tint = 500 s • Detector polarization: Vdet= 60 V 5.9 mV/MIP Pedestal value =69.9 mV ; pedestal width = 21.1 mV First signal peak= 75.8 mV; signal peak width = 21.8 mV AGH-University of Science and Technology & Institute of Electron Technology, Poland

13. Preliminary tests with the laser light • Laser light not focused, shining from the backplane • Wavelength = 850 nm • 5 s wide light pulses -each corresponding to 2.1 MIP • Integration time = 500 s • Detector polarization=60V • 1000 events recorded and averaged Good detector sensitivity for the ionizing radiation and linear response as a function of the generated charge was observed. AGH-University of Science and Technology & Institute of Electron Technology, Poland

14. Layout solution of the final size sensor Basic segment: 64 x 64=4096 channels Dimensions:12 x 12 mm2 Cell dimensions:160x160m2 Complex of 4 rotated and flipped chips: Dimensions: 24 x 24 mm2 4 parallel outputs 128 x 128 = 16 384 channels Ladders: Dimensions: up to 72x24 mm2 Small dead areas AGH-University of Science and Technology & Institute of Electron Technology, Poland

15. Architecture of the final SOI sensor The architecture exercised on the prototype chip will be implemented in the final SOI sensor design • Readout scheme compatible with external CDS but sequence is not conventional • Short detector dead time and well defined integration time AGH-University of Science and Technology & Institute of Electron Technology, Poland

16. Verification of the readout scheme - prototype front-end electronics Example of Data Acquisition and Analysis • Test set-up: 12 bit ADC with input range of 5V and dedicated software running under LabVIEW • Test signal corresponding to about 3 MIP injected into every forth channel • CDS processing: effective signal = sample after integration time – sample after reset • Threshold voltage: 3 ADC counts • Maximum readout speed: 1 MHz – limited by analogue part AGH-University of Science and Technology & Institute of Electron Technology, Poland

17. Conclusions Current stage of the project • First small area SOI pixel sensors have been fabricated. • Preliminary tests with laser light and radioactive source have indicated high detector sensitivity for the ionising radiation. Detailed tests with a focused laser spot will be carried-on nearest weeks and allow to study charge generation and sharing mechanisms for the new sensor. • Readout architecture has been exercised with the usage of the prototype front-end electronics designed in commercial technology. • Satisfactory results of the tests of the small readout matrices on the SOI test structures and prototype chips are a starting point for the design of the fully functional and large area SOI sensor. • The design of the final SOI sensor will be completed next year. AGH-University of Science and Technology & Institute of Electron Technology, Poland