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Fast SPICE Simulators: A Survey

Fast SPICE Simulators: A Survey. Outline. How SPICE works Fast SPICE simulators in the market Nassda’s HSIM Avant!’s Star-SimXT and more More on HSIM. SPICE. Really, it’s just all about solving KCL and KVL equations: Generally, it’s a nonlinear differential equation (e.g. transistors).

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Fast SPICE Simulators: A Survey

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  1. Fast SPICE Simulators: A Survey

  2. Outline • How SPICE works • Fast SPICE simulators in the market • Nassda’s HSIM • Avant!’s Star-SimXT • and more • More on HSIM Jaeha Kim, 10/17/2001

  3. SPICE • Really, it’s just all about solving KCL and KVL equations: • Generally, it’s a nonlinear differential equation (e.g. transistors). • Bunch of numerical algebra Jaeha Kim, 10/17/2001

  4. First, Linearize it • At each time step, SPICE builds a small-signal model (i.e. linear model) at the operating point: Jaeha Kim, 10/17/2001

  5. Matrix Equation • Construct a matrix equation : Ax=b Jaeha Kim, 10/17/2001

  6. Then, Solve Ax=b • Direct Method: x = A-1b. • Iterative Method: xn+1 = f(xn); iterate until xn converges to the solution. • Example: b = 1/a vs bn+1 = bn(2-a.bn). Jaeha Kim, 10/17/2001

  7. Ways to speed up • Speed bottlenecks: • Small circuits: linearizing • Large circuits: solving equations • Recent techniques for speed-up: • Look-up table model • Event-driven algorithm or multi-timestep algorithm: less computation for inactive subcircuits • Hierarchical simulation: save memory and computation for redundant circuits. • Parallel computation Jaeha Kim, 10/17/2001

  8. Cadence’s Spectre • 3x faster than SPICE • Can handle up to 50,000+ devices • Uses the same basic algorithms as SPICE; just written more carefully with the latest algorithmic techniques. • Behavioral description (Verilog-A) Jaeha Kim, 10/17/2001

  9. Cadence’s ATS • Accelerated Transistor-Level Simulator • 100-1,000x faster than SPICE within 5% error • Partitions the circuits and uses different time-steps: exploits circuit latency and multi-rate behavior Jaeha Kim, 10/17/2001

  10. Celestry’s UltraSim • 100-1,000x faster than SPICE within 1% error • Hierarchical simulation: adaptive-hierarchy compaction technology  crucial for DRAM simulation • Faster ODE solver engine Jaeha Kim, 10/17/2001

  11. Synopsys’s NanoSim • 10-1,000x faster than SPICE within 2-7% error. • Used with TimeMill and PowerMill. • Hierarchical Array Reduction(HAR) • Analog Circuit Engine(ACE): partitioning and synchronization (parallel comp.). • Verilog-A support Jaeha Kim, 10/17/2001

  12. Nassda’s HSIM • Hierarchical Storage and Isomorphic Matching • 1,000-10,000x faster than SPICE with user-selectable accuracy • Hierarchical storage and simulation • Isomorphic matching: duplicate simulated circuit response for isomorphic subcircuits under same conditions. • Does not use simplified model or simulation algorithms. Jaeha Kim, 10/17/2001

  13. Avant!’s Star-SimXT • Successor to Star-Sim (old: Anagram) • 10,000x faster than SPICE with 0% error • Uses exactly the same models as Hspice (no more table-based models). • Hierarchical simulation (Dynamic-Hierarchy Engine) • Multi-threading simulation kernel (4x speed up on multi-CPU machines) Jaeha Kim, 10/17/2001

  14. Some HSIM Tips • User-Selectable Accuracy • Logic Functional Verification • Timing and Power Checks Jaeha Kim, 10/17/2001

  15. Accuracy Options in HSIM • Can individually set for each subcircuit or instance: .param subckt=pll inst=Xpll HSIMparam=<value> • HSIMSPEED: choose speed-up mechanisms  0 (accurate) ~ 6 (fast) (see the manual). • HSIMSPICE: model accuracy  0 (table model), 1 (DC model), 2 (AC model). • HSIMANALOG: coupling between subcircuits  0 (no coupling), 1 (coupling within hierarchical boundary), 2 (coupling across the boundary). Jaeha Kim, 10/17/2001

  16. Functional Verification • Spice deck: .param HSIMVECTORFILE = ‘hsim.vec’ • Vector file (hsim.vec): signal clk pd_out[1:0] phdir phwt_0 phwt_14 + phsel_up phsel_dn phwt_up phwt_dn toggle_dir period 10 radix 111111 11111 io iiiiii ooooo 110111 00000 010111 00000 110111 00000 ……… Jaeha Kim, 10/17/2001

  17. Assertion Checks • Timing checks: setup, hold, pulse-width, and delay. .tcheck check1 setup D x ck r 100ps • Power checks: DC path, excessive current, excessive rise and fall time, and high-impedance node. .pcheck check2 exrf Q rise=200ps fall=200ps Jaeha Kim, 10/17/2001

  18. Some Observations • The fundamentals never change: still solving the equation Ax=b. • Fast SPICE is cool, but the market is small ($200-300 million). • Will it continue to evolve?  Yes, cheaper than hiring a circuit designer. • Future directions:  More parallel computation  Better user-interface / post-sim analysis Jaeha Kim, 10/17/2001

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