'Elmore delay' diaporamas de présentation

Prof. Lei He Electrical Engineering Department University of California, Los Angeles

Chapter 2 Interconnect Analysis Delay Modeling. Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe@ee.ucla.edu. Outline. Delay models RC tree Elmore delay Gate delay Homework 2. Input-to-Output Propagation Delay.

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Revisiting Fidelity: A Case of Elmore-based Y-routing Trees

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Revisiting Fidelity: A Case of Elmore-based Y-routing Trees

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Prof. Lei He Electrical Engineering Department University of California, Los Angeles

Chapter 2 Interconnect Analysis Delay Modeling. Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe@ee.ucla.edu. Outline. Delay models RC tree Elmore delay (First Order) Second Order Analysis (S2P algorithm) Gate delay.

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ECE 124a/256c VLSI RC(L) Interconnect Models

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The Wires

EE4271 VLSI Design. Dr. Shiyan Hu Office: EERC 731. The Wires. Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Modern Interconnect. Modern Interconnect - II. Interconnect Delay Dominates. 300.

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The Wires

EE4271 VLSI Design. Dr. Shiyan Hu Office: EERC 518. The Wires. Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Modern Interconnect. Modern Interconnect - II. Interconnect Delay Dominates. 300.

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Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response. Outline. Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation. Pass Transistors. We have assumed source is grounded What if source > 0? e.g. pass transistor passing V DD V g = V DD

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Chapter 2 Interconnect Analysis

Chapter 2 Interconnect Analysis. Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe@ee.ucla.edu. Organization. Chapter 2a Linear System First Order Analysis (Elmore Delay) Second Order Analysis

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Performance-Impact Limited Area Fill Synthesis

Supported by Cadence Design Systems, Inc. and MARCO/DARPA GSRC. Performance-Impact Limited Area Fill Synthesis. Yu Chen UbiTech, Inc. Puneet Gupta, Andrew B. Kahng Univ. of California, San Diego http://vlsicad.ucsd.edu. Outline. Chemical Mechanical Planarization and Area Fill

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Routing

Routing. Prof. Shiyan Hu shiyan@mtu.edu Office: EERC 731. Interconnect Topology Optimization. Problem: given a source and a set of sinks, build the best interconnect topology to minimize different design objectives: Wire length: traditional (lower capacitance load, and overall congestion)

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Chapter 4 Interconnect Analysis

Chapter 4 Interconnect Analysis. Organization. 4.1 Linear System 4.2 Elmore Delay 4.3 Moment Matching and Model Order Reduction AWE PRIMA 4.4 Recent development MOR for network Parameterized MOR. Reading Assignment for 4.1 and 4.2.

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Interconnect Optimizations

Interconnect Optimizations. G. S. D. w. S. h. l. h s. l s. S s. w s. A scaling primer. Ideal process scaling: Device geometries shrink by S ( = 0.7x) Device delay shrinks by s Wire geometries shrink by s R/ m : r /(ws.hs) = r/s 2 Cc/ m : (hs). e /(Ss) = Cc C/ m : similar

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Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review

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CEG3470 REVISION LECTURE (Some slides from Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response)

CEG3470 REVISION LECTURE (Some slides from Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response). David Harris Harvey Mudd College Spring 2004. Outline. Transistor capacitances Transistor properties (current & capacitance vs size & voltage)

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Elmore Routing Tree (ERT) Algorithm

Elmore Routing Tree (ERT) Algorithm. Perform ERT algorithm under 65 nm technology Unit-length resistance r = 0.4 ? / ? m Unit-length capacitance c = 0.2 f F / ? m Driver output resistance r d = 250 ? Sink input capacitance r = 50 f F. Adding First Edge.

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Pass-Transistor Logic

Pass-Transistor Logic. NMOS-only switch. Solution 1: Transmission Gate. Resistance of Transmission Gate. S. S. Pass-Transistor Based Multiplexer. S. V DD. GND. In 1. In 2. S. Transmission Gate XOR. Delay in Transmission Gate Networks. Elmore Delay (Chapter 8). Delay Optimization.

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Pass-Transistor Logic

Pass-Transistor Logic. NMOS-only switch. Solution 1: Transmission Gate. Resistance of Transmission Gate. S. S. Pass-Transistor Based Multiplexer. S. V DD. GND. In 1. In 2. S. Transmission Gate XOR. Delay in Transmission Gate Networks. Elmore Delay (Chapter 8). Delay Optimization.

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Pass-Transistor Logic

Pass-Transistor Logic. NMOS-only switch. Solution 1: Transmission Gate. Resistance of Transmission Gate. S. S. Pass-Transistor Based Multiplexer. S. V DD. GND. In 1. In 2. S. Transmission Gate XOR. Delay in Transmission Gate Networks. Elmore Delay (Chapter 8). Delay Optimization.

431 views • 15 slides