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HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14. Supervisor: Moni Orbach. Students: Or Rotem Malachi Levi. Project goals. Implementing cordic algorithm in VHDL environment Investigating different acceleration methods

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273 views • 15 slides

Quick Starting Guide to ModelSim SE 5.5a Verilog & VHDL Simulator

Quick Starting Guide to ModelSim SE 5.5a Verilog & VHDL Simulator. By: Amir Masoud Gharehbaghi Email: amgh@mehr.sharif.edu. General Info. ModelSim is a VHDL and Verilog simulator by Model Technology Inc. www.model.com. Software Location.

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137 views • 13 slides

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HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Quick Starting Guide to ModelSim SE 5.5a Verilog &amp; VHDL Simulator

Quick Starting Guide to ModelSim SE 5.5a Verilog & VHDL Simulator