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Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in Embedded Processors

Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in Embedded Processors. Houman Homayoun, Avesta Makhzan, Alex Veidenbaum Dept. of Computer Science, UC Irvine hhomayou@ics.uci.edu. On-chip Caches and Power . On-chip caches in high-performance processors are large

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Peripheral circuits - PowerPoint PPT Presentation

Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in Embedded Processors