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Series Scheme Charge Pumps Plans

DC to DC Power Converion R. Ely and M. Garcia-Sciveres Atlas Upgrade Workshop Santa Cruz, November 2005. Series Scheme Charge Pumps Plans. Higher voltage power distribution is a MUST. Read: voltage delivery at n times operating voltage. SCT SLHC. (from Marc Weber’s Genova workshop talk).

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Series Scheme Charge Pumps Plans

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  1. DC to DC Power ConverionR. Ely and M. Garcia-Sciveres Atlas Upgrade WorkshopSanta Cruz, November 2005 • Series Scheme • Charge Pumps • Plans UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  2. Higher voltage power distribution is a MUST Read: voltage delivery at n times operating voltage SCTSLHC (from Marc Weber’s Genova workshop talk) UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  3. Two Options • Serial Power • Work started with Pixels. Demonstrated with present modules by Bonn group • Picked up for SCT modules by Marc Weber at RAL • Will be incorporated into stave prototypes • DC-DC converters • Proposed by LBNL • Initial simulations shown at Genova (details later) • No prototype yet due to lack of IC designer availability UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  4. First of all: Serial powering applies tomodules, that is groups of chips on one hybrid connected to one sensor. Within hybrid, chips are powered in parallel ! • one current source for a chain of modules; voltage defined by set of regulators • “ground levels” of any pair of modules vary UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  5. RAL work (Mark Weber) 4 SCT modules, serial powering PCBs, DAQ support cards M4 M3 DAQ support card Serial powering PCB M2 DAQ support card Serial powering PCB SCT module 1 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  6. Schematics of serial powering PCB UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  7. Photograph of serial powering PCB Analog regulator Shunt regulator AC LVDS Clock and command AC LVDS data DAQ support card SCT module UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  8. Noise performance: indep. vs. serial powering Let’s look at noise occupancy (NO) first Module 662 powered independently Module 662 powered in series with 3 others Noise performance remains excellent ! UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  9. Noise performance: independent powering vs. serial powering Independently powered Powered in series Noise performance remains excellent UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  10. Noise performance: independent powering vs. serial powering Independently powered | Powered in series Noise performance remains excellent UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  11. Serial SCT plans from Genova • More studies on SCT module set-up (1-3 months) • more noise tests e.g. introducing noise sources/ oscillations • closer look into AC-LVDS coupling • Built and study a more realistic system(½ -2 years) • Dense packaging; • Grounding and shielding issues • Miniaturized regulator circuitry; • Modified readout chip • Redundancy features • If promising, develop SLHC prototype (> 2 years) UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  12. DC-DC Converter options • Switched Capacitor array • not common in industry except for divide by 2 • Seems natural choice for us- fewer worries (see below). • Inductor Buck converter • typical in industry • We would have to worry about magnetic field, EMI from fringe fields, and would have to make our own air-core toroidal inductors. UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  13. Vd Vd + + + + + + + + + + + + - - - - - - - - - - - - 1 1 1 1 2 2 2 2 2 2 Load Load Load Divide by 4 Stack 4 capacitors – 13 switches • Phase 1 • Phase 2 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  14. 1 2 2 1 VS VS Z 2 1 2 C0 C3 C1 C2 1 1 2 C3 C1 3V C2 V C2 V 2V C3 5V C1 C0 DC Converter - DC4x5 DC converter with 4 caps and an ideal conversion ratio of 5 10 switches Phase 1 Phase 2 C0 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  15. VS VS 1 2 2 2 1 2 1 1 C5 C4 C2 C3 C4 C0 C5 C1 C4 C2 C0 C1 C3 C5 C3 C2 C1 C0 Z Phase 1 6 Capacitors 8 Switches DC Converter – Div by 4 Ladder Phase 2 UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  16. Comparison of CircuitsNormalize to Divide by 5 • Stack 5 caps 16 switches • Uniform charge on caps • Large voltage swings on switches • DC4x5 4 caps 10 switches • 2 caps have potential of 3Vo • Lower voltage swings on switches • Ladder 10 caps 12 switches • Larger potential differences on caps • Voltage swings on switches ~ Vo UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  17. CMOS Transistor Switches • Austria Microsystems H35 Process • Feature size 0.35μ • 3 gate oxides • Vds up to 50 vts • Bulk isolation • Gate oxide breakdown vt > 8vts UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  18. AMS H35 Transistors UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  19. Figures of Merit(for divide by n) • Voltage efficiency - εv = n*Vout / Vin • Vout is a function of the load = Vin / n for no load • Current efficiency - εI = Iout / n*Iin • Charge is lost charging the gate capacitance of the switches • Power efficiency - εp = εv * εI • Ripple - less than Iout*period/C UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  20. Figures of Merit for Divide by n Stack Supplying Io (all switches have ‘on’ resistance R, all switched capacitors have value C and Co >>C) • Low frequency limit – RC << 1/f • Hi frequency limit - RC >> 1/f - clearly we want IoR << Vs/4 (for Vs = 10v, R < 2.5Ώ (For ladder) UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  21. Divide by 5Stack UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  22. Drain-Gate-SourceWaveforms of Switches UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  23. Efficiency versus Frequency UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  24. Efficiency vs Transistor Width UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  25. Power Efficiency UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  26. Buck Converter UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  27. DC Conversion Conclusions • At an operating freqency of 5mhz (Co = 4.7uf, C1 = 0.2uf • Voltage efficiency ~.84 • Current efficiency ~.92 • Ripple = 1.2% • Output impedance = 0.25 ohms (25mv / 100ma) • Clock generator will reduce efficiency by 10% UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  28. Other topics not related to power UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  29. Test of Indium Bumped “2E” Assembly 2E = 2 columns per pixel. Only a small region of the sensor is properly bonded to the readout chip. The rest of the pixels are disconnected. The bonded region is shown here. X-axis is column number and Y-axis is row. Only the bonded channels were probed in what follows. Disconnected channels were masked off. Mask used for scans UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  30. Noise vs. Voltage Low voltage values not reliable due to bad S-curve fits This is the most probable single channel noise for select connected pixels. Determined from s-curve fits in charge injection scans after tuning thresholds to 4000e. Looks like Depletion voltage at ~23 V UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  31. Representive S-curves at varying voltages Above depletioon voltage (~25 V) 12 V 6.5 V 3.5 V 2.0 V 0.5 V Corrected bias voltage UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  32. Short strip module geometry For a given hybrid technology, only way to reduce ratio (hybrid_mass)/(silicon mass) is to increase IC input density Hybrid can neck down here to save mass Sensor is twice the strip length, With bond pads in the middle. IC hybrid sensor stave UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

  33. Nanowire carpet hybrid pixel proposal • Submitted to LBNL molecular foundry • Too recent to know where this will go • Eliminates bump bonding AND sensor wafer patterning. • Intent is to produce very cheap hybrid pixel modules. UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres

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