Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege

1. Engineering 43 Sequential (FlipFlop) Logic Bruce Mayer, PE Licensed Electrical & Mechanical EngineerBMayer@ChabotCollege.edu

2. But First… WhiteBoard Work • For the Truth Table Shown at right • Construct the Karnaugh Map • Write The Minimized Function Q(A,B,C,D) • Draw the Logic Circuit • Notice “1’s” in Rows • 1, 5, 9, 13, 14, 15 • Need only put “1’s” in these locations; other cells Assumed to be Zero

3. Blank Map (NonStretching)

4. Stretchable Blank Map

5. More… WhiteBoard Work • Implement This Function using ONLY NAND Gates • An Example of NAND-Gate Synthesis • NANDS are easier to construct than ANDs, ORs, NORs • NANDs are the preferred gate for logic circuits

6. “Memory Filled” Logic • The Invert/AND/OR Combinatorial Logic Circuits depended ONLY on the Current Inputs; previous states did Not affect the Current State • Combinatorial Logic is MEMORYLESS • In SEQUENTIAL Logic the Circuit Output CAN Depend on the Previous condition of the Circuit • Sequential Logic has MEMORY

7. Combinational outputs Memory outputs Combinational logic Memory elements External inputs Sequential Circuit • A sequential circuit consists of a feedback path, and employs some memory elements • [Sequential circuit] = [Combinational logic] + [Memory Elements]

8. Synchronous vs Asynchronous • Almost all Logic “Chips” Include a Clock • The Clock helps to “Synchronize” the Operation of the Circuits. • The “Clock” is simply a very regular Hi/Lo Pulse train  • Logic Forms are divided into two groups: • SYNCHRONUS → Depend on Clock • Asynchronous → NO Clock-Dependency

9. Q R 0 1 0 1 S R R R R Q Q Q Q Q' Q' Q' Q' S S S S 0 0 1 1 Asynchronous S-R FlipFlop • Cross-coupled NOR gates • Similar to inverter pair, with capability to force Q to 0 (reset=1) or 1 (set=1) 0 1 1 n-1 ?? 0 n-1 ??

10. Q S' S' R' Q Q' R' NAND based SR FlipFlop • Cross-coupled NAND gates • Similar to inverter pair, with capability to force Q to 0 (reset=0) or 1 (set=0) NOR notes NAND notes • Any HI input → LO output • Any HI → LO • All LO inputs → HI output • All LO → HI • Any LO input → HI output • Any LO → HI • All HI inputs → LO output • All HI → LO

11. R Q Q' S SRQn-1Qn0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 X hold reset set not allowed State Behavior of SR FlipFlop characteristic equation Qn= S + R’∙Qn-1 • Transition Table • Sequential (output depends on history when inputs R=0, S=0) but asynchronous REset SET

12. R Q Q' S SR FlipFlop Timing Behavior • Any HI input → LO output • Any HI → LO • All LO inputs → HI output • All LO → HI Hold Race Reset Set Reset Set 100 R S Q Q’ • “Races” Produce UnPredictableOutPuts

13. Clocked SR FlipFlop • Control times whenR and S inputs matter • Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored • Ensure R & S stable before utilized (to avoid transient R=1, S=1)

14. Clocked SR FlipFlops • NOR-NOR Implementation • TruthTable • For NOR: any-Hi→LO; ALL-LO→Hi

15. Clocked SR FlipFlops • NAND-NOR Implementation • TruthTable Circuit Symbol

16. SR FlipFlop Clock-Overide • Sometimes Need to Set or Reset the FlipFlopwithOUT Regard to the Clock • Note the position of Pr & Cl on the 3rd-Stage ORs (any Hi→Hi) • Ensures Pr & ClOverRide R, S, & C

17. D’ D 0 R Q Clk=1 Q’ S 0 D’ D Edge Triggered D FlipFlop • sensitive to inputs only near edge of clock signal (not while steady ) holds D' when clock goes low holds D whenclock goes low

18. Edge-Triggered FlipFlop Flavors • POSITIVE edge-triggered • Inputs sampled on RISING edge; outputs change after RISING edge • NEGATIVE edge-triggered flip-flops • Inputs sampled on falling edge; outputs change after falling edge 100 D CLK Qpos Qpos' Qneg Qneg' positive edge-triggered FF negative edge-triggered FF

19. Edge Triggered D FlipFlop • 4-NAND, 1-NOTimplementation • Truth Table for All Postive-GoingEdge D-FF’s • NAND: • any LO → Hi • All HI → LO

20. Edge Triggered JK FlipFlop • A “Toggling” Flip Flop • Under A certain Control-Set: Q → Q’ • Notice that Q does NOT go HI-for-sure or LO-for-sure, and it does NOT remain STEADY • A NAND Nest: • Circuit Symbol

21. JK FlipFlop Toggle TruthTable • The Simplified Ckt • Note that the outputs feed back to the enabling NAND gates. This is what gives the toggling action when J=K=1 • ReCall NAND • Any LO → Hi • ALL Hi → LO

22. Q0 Q1 D D Q Q IN OUT CLK Cascading FF → Shift Register • Serial-in/Parallel-out Shift register • New value goes into first stage • While previous value of 1ststg goes into 2ndstg • The QN can be SAMPLED any time

23. Clocked Synchronous Synchronizer System Q0 Async Q0 Async Input Input Clock Clock Q1 Q1 D Q D Q D Q Clock Clock D Q D Q Example: Eliminate Inconsistency Want to Send SAMEInput Value to TWO Places In Q0 Q1 CLK is asynchronous and fans out to D0 and D1one FF catches the signal, one does not inconsistent state may be reached!

24. FlipFlops Summarized • Development of D-FF • Level-sensitive used in custom integrated circuits • can be made with 4 pairs of gates • Usually follows multiphase non-overlapping clock discipline • Edge-triggered used in programmable logic devices • Good choice for data storage register

25. FlipFlops Summarized • Historically J-K FF was popular but now never used • Similar to R-S but with 1-1 being used to toggle output (complement state) • Same Operation Can always be implemented using D FlipFlops • Preset and Clear inputs are highly desirable on flip-flops • Used at start-up or to reset system to a known state

26. FlipFlops Summarized • Reset (set state to 0)  R • Synchronous: Dnew = R' • Dold • Transition only when next clock edge arrives • Asynchronous: doesn't wait for clock, • quick but dangerous • Preset or Set (set state to 1)  S • Synchronous: Dnew = Dold + S • Transition only when next clock edge arrives) • Asynchronous: doesn't wait for clock • quick but dangerous

27. WhiteBoard Work • Use Gates and a D-FF to Implement the JK-FF operation

28. All Done for Today IEEE91-1984Gates

29. Engineering 43 AppendixLogic Syn Bruce Mayer, PE Licensed Electrical & Mechanical EngineerBMayer@ChabotCollege.edu

32. NAND Gate Synthesis • With the expression in SOP form • After any need inversions; In the first logic level there are as many logic gates as terms in the SOP expression • Each gate corresponds to a SINGLE Term, and has, as inputs, the variables in that term • The outputs of the First Logic-Level are ALL inputs to a SINGLE (multi-input if needed) NAND gate