1 / 11

Top Level Simulation

Top Level Simulation. Top Level Simulation with All Parasitics. Sample at CKAD. Sampled FPUout. x1 Output. Reconstruct I. Subtract Ped., Gains (from sim) 1, 4.95, 8.95, 32.8 ( ± calc. err). Reconstruct II. Shift by dt = 13 ns. Understanding the Results. Evaluate Settling time

takoda
Télécharger la présentation

Top Level Simulation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Top Level Simulation Top Level Simulation with All Parasitics

  2. Sample at CKAD Sampled FPUout x1 Output

  3. Reconstruct I. Subtract Ped., Gains (from sim) 1, 4.95, 8.95, 32.8 (± calc. err)

  4. Reconstruct II. Shift by dt = 13 ns

  5. Understanding the Results Evaluate Settling time and Resolution 1.5 TeV Input - Worst Case

  6. Plot Modulo 25 ns Track Hold ADC

  7. Mod 25 ns - <Hold Plateau> ADC Settling Time SH Clock Feed through Data are at 1 mV precision

  8. Interpretation =450 µV (11 bits)

  9. FPU Logic Inputs

  10. Logic Input Transfer Function

  11. Conclusions • Complex chip: not so many transistors, but high demands on performance • Parasitic resistance really does seem to be the cause of the problems we had with FPPA2000 • FPPA2000 noise reproduced in simulation • Layout optimizations • Some circuit tweaks • Top-level simulations with all parasitics predict performance which meets specs • Consider preparation for verification and test

More Related