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Sector Logic Implementation for the ATLAS Endcap Level-1 Muon Trigger

Sector Logic Implementation for the ATLAS Endcap Level-1 Muon Trigger. R. Ichimiya (Kobe university). Contents ATLAS Level-1 Trigger system Endcap Muon Trigger system Sector Logic Design Prototype Test Results Summary. ATLAS Trigger and DAQ system. Level-1 Trigger System.

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Sector Logic Implementation for the ATLAS Endcap Level-1 Muon Trigger

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  1. Sector Logic Implementation for the ATLAS Endcap Level-1 Muon Trigger R. Ichimiya (Kobe university) Contents ATLAS Level-1 Trigger system Endcap Muon Trigger system Sector Logic Design Prototype Test Results Summary 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  2. ATLAS Trigger and DAQ system Level-1 Trigger System ATLAS Trigger & DAQ System 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  3. Muon Trigger system Muon Trigger Chambers Muon Trigger: based on momentum measurement in the magnetic field. Trigger Chambers: • For endcap region (|h| >1.05): Thin Gap Chamber(TGC) • For barrel region (|h| <1.05): Resistive Plate Chamber(RPC) |h| =1.05 R B Interaction Point (IP) Z 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  4. Endcap Muon Trigger TGC layout Endcap Muon Trigger finds muon’s tracks using 7 layers of TGC detectors. 3TGCs(M1)+2TGCs(M2)+2TGCs(M3) measures deviations from straight line to IP. (dR, df) => pT(transverse), charge Two kind of coincidence: • Low-pT(2-station coincidence) • High-pT(3-station coincidence) EI/FI is innermost TGCs to suppress fake muons, and low-momentum background muons . dR B 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  5. Endcap Muon Trigger Electronics Stage1 (low-pT block) • 2-station coincidence between the hits in the Doublets. Stage2 (high-pT block) • 3-station coincidence between Low-pT and the hits in the Triplet. Measure dR, df in parallel. 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  6. Endcap Muon Trigger Electronics Stage3 (Sector Logic) combines R- and f-informaton from high-pT coincidence. • Reconstruct 3-dimensional muon tracks. • tag with its pT value of 6 levels by using dR and df. • choose 2 highest pT tracks. 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  7. Trigger Sector An Sub-Sector is a unit for position of tracks (RoI). An Trigger Sector is a segment of the trigger electronics. • 96 Endcap Trigger Sectors (|h| <2.06) • 48 Forward Trigger Sectors (|h| >2.06) consists of • 148 Sub-Sectors (Endcap Trigger Sector) • 64 Sub-Sectors (Forward Trigger Sector) 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  8. ATLAS Troidal Magnets Hitmap on the TGC for the same pT muons Map of Magnetic Fields Non-uniformity of magnetic field dR and df vary point by point. To keep momentum resolution high, We divide TGC plane into sub-sectors, where pT measurement is performed independently. 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  9. Track Finding & pT measurement Track Finding scheme • Input: (R, dR)+(f, df) • Up to 1 hit input among 2 adjoining sub-sectors. • Find track hit position. • calculate its pT and charge • Suppress fake tracks by selecting higher pT track for same R position. We adopt Look-up Table(LUT) method to realize the Track Finding logic. 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  10. Implementation using LUT An SSC block using LUT • Each LUT covers 8 sub-sectors; sub-sector cluster (SSC). • Receives a R input (R, dR), 2 f inputs(f, df). • Input: 19bit, • Selects the highest pT track in a SSC. • Output: 4bit. • There are: • 23 SSCs (Endcap Trigger Sector) • 8 SSCs (Forward Trigger Sector) LUT 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  11. Track Selection Logic Track Selection Logic scheme • Track Selection Logic selects 2 highest-pT tracks from the SSC outputs. • Divide into 2 stages: • 6 Pre-Selectors: • Collects same pT tracks and choose 2 lowest h tracks. • Final-Selector: • Picks up 2 highest pT tracks among 12 candidates of 6 pre-selectors. h 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  12. Sector Logic Functionalities Track Finding & pT measurement 1. Find track hit position in a sub-sector by combining both inputs(R, f). 2. pT measurement in 6 levels at each 8 sub-sectors(SSC). Track Selection Logic choose 2 highest pT tracks in a trigger sector. Requirements: • Can operate in 40MHz synchronously with no-dead-time. • Flexibility for changing algorithms. => Employs FPGA with pipelined structure. 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  13. Prototype-0: FPGA(Virtex-EM) • Device Choice • Large SRAM embedded type FPGA is required to hold many big LUTs. • Xilinx Virtex-EM series (XCV405E) • BlockRAM™ 560Kbit • synchronous SRAM • 4Kbit x 160 • (cf. 82Kbit in XCV400E as same gate size) • Merits • Can access the LUT very fast. (access speed: 2.46ns) • Reduce number of chips and wiring in PCB board. • (!) Needs 1 additional clock cycle to access the BlockRAM™. (Because, the BlockRAM™ is the synchronous SRAM.) 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  14. Block Diagram of the Sector Logic Block diagram of the Sector Logic • Pipelined structure components • Decoder • R-f Coincidence • De-multiplexer • Pre-Selector • Final-Selector • Encoder • Readout buffer 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  15. Prototype-0 Photograph of the Prototype-0 Fully functional sector logic for forward trigger sector. • For validation of the sector logic design. Specifications: • VME64x (9Ux400mm) slave module. • 3 optical input links (50bit in total). • 3 Virtex series (Xilinx) FPGAs. • 32bit LVDS output to MUCTPI. • Power consumption: ~7W (~2.2A@3.3V). 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  16. Block diagram of the Prototype-0 Block diagram of the Prototype-0 • Implement the core in a set of 3 FPGAs. • In 2 SRAM embedded FPGAs: (XCV405E) • Decoder • R-f Coincidence • In a FPGA: (XCV400E) • Pre-Selector • Final-Selector • Encoder • Peripheral Blocks: • Optical Interface • G-Link (Agilent) • OE/EO converter (Infineon) • Readout Buffer • SLB ASIC (developed for Stage1) 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  17. Performance Test (timing margin) data path Setup • Input Data: • Data were fed through Optical Link (20m) with G-Link Serializer. • Output Data: • Read out by FIFO module, instead of MUCTPI. (*) Input and Output are synchronized to 40.08MHz. Result Can operate up to 51.5MHz. timing margin > 5.5ns(@40MHz) 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  18. Performance Test (functional check) Setup Result • Outputs are compared with the test vectors which generated by the simulator. • 1.3M events were tested. No error were found. Generate muon tracks (up to 6 tracks). Simulate these blocks for generating Test Vectors fed to the Sector Logic. 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  19. Integration Test with the MUCTPI Setup • SL was configured as an PPG. • TTCvi was used for clock source (40.08MHz), Trigger(L1A) for MIOCT. Result Error rate: <10-9 /bit. 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

  20. Summary • Designed the Sector Logic for endcap muon trigger. • The core is R-f coincidence and Track Selection Logic. • SRAM embedded FPGA for the LUT of R-f coincidence. • Pipelined structure. • Fabricated and Tested fully functional Sector Logic Prototype. • FPGA based design. • It worked up to 51.5MHz; 5.5ns margin @40MHz. • No error with 1.3M input patterns. • Verified the data transmission from the Sector Logic to the MUCTPI. The design and the prototype implementation satisfies requirements for the endcap muon Sector Logic. 8th Workshop on Electronics for LHC Experiment, Colmar, France, 10 Sep. 2002 R.Ichimiya, ATLAS Japan

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