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Development of the ATLAS Endcap Muon Trigger Electronics

Development of the ATLAS Endcap Muon Trigger Electronics. Status Report of the “Slice Test”. Japan Physics Society Meeting, 2003 Spring 28-31/Mar, Tohoku Gakuin Univ., Sendai, Japan. Kunihiro Nagano (CERN) on behalf of the ATLAS Japan TGC Electronics Group. The “Slice Test”.

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Development of the ATLAS Endcap Muon Trigger Electronics

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  1. Development of the ATLAS Endcap Muon Trigger Electronics Status Report of the “Slice Test” Japan Physics Society Meeting, 2003 Spring28-31/Mar, Tohoku Gakuin Univ., Sendai, Japan Kunihiro Nagano (CERN)on behalf of the ATLAS Japan TGC Electronics Group

  2. The “Slice Test” • Development of custom ASICs: • Design works almost finalized. • Prototypes with full specification produced. • Stand-alone tests done. “Slice Test” = Integration and system-wide tests of full components

  3. ~15m ~90m • Trigger Path • Read-out Path • Control Path TGC Trigger Electronics System Data from Chamber Experimental Hall The system has:

  4. PS Board Slave-board (SLB)ASIC • Find low pT candidates by taking coincidence between 2 outer chamber stations • R and φ processed independently Patch-Panel (PP) ASIC • Latch data from chambers and synchronize them to 40.08 MHz clock (bunch crossing identification) • Fine timing adjustment

  5. HPT Board, SL Board Sector Logic (SL) Board • R-φ coincidence, pT determination • Implemented with FPGAs High-pT (HPT) ASIC • Find high-pT candidates by taking coincidence between hits in the inner most chamber station and low pT candidates • R and φinformation are processed indenpendently

  6. Setup Data flow • Input: Pulse-Pattern-Generators (PPGs). Test vectors were loaded into PPGs. • Output: a general-purpose FIFO (TOM) was used to read-out SL output. • Clock: provided by the Trigger, Timing, Control system (TTC) • A set of Wire (R) and Strip (φ) PS Boards. • One HPT Module • One SL Module

  7. Setup -cont’d- Corresponds to

  8. Functional Test Result • No error in comparison to simulation with: 1-Track: 10 K vectors, 2-Track: 10 K vectors

  9. Performance Test Result [Latency] (See H.Kano, LECC 2002, Colmar) • Latency is within the budget !

  10. Slice Test 2003 [What’s On-going ?] • New PS Boards with new versions of PP, SLB, JRC ASICs • PP ASIC • 16 ch →32 ch • Rohm CMOS 0.6 → 0.35 μm process • SLB ASIC • JTAG bug fix • JRC ASIC • CPLD → ASIC • Strip: verified with ~500 vectors up to HPT output. • Wire: mismatch exists at ~10% level. Debugging on-going. Integrated into theSlice Test System

  11. Slice Test 2003 -cont’d- • Star-Switch (SSW): full spec. prototype was produced • Control Path: HSC-CCI via SSW established • Readout Path: being tested. • Read-out Driver (ROD): ready • Connection to higher DAQ (ROB via S-Link) established Trigger + Read-out + Control at: • Chamber Integration Test at Cosmic-Ray Station (Kobe Univ.) in Mar. 2003 • Test-beam at CERN in May 2003

  12. Chamber Integration at Kobe (10-14 Mar., 2003) Chamber Elec. Connected by LVDS 40-twisted pair cables

  13. Doublet PS Board Doublet Triplet TTC SPP SSW • PP ASIC Output (OR of 32 channels) • Raw Trigger Signal (NIM) • Trigger Signal in PS Board (L1A after TTC) Chamber Integration Results Scintilator hodoscope (Trigger) • First connection between analogue and digital (it is always not trivial !) • No oscillation was observed at all. • Applying threshold for ASD worked fine.

  14. Summary • Slice Test • Functional Test: verified with ~10 K test vectors each of 1-Track and 2-Track events • Performance Test: latency was measured as 1176 ns, which is less than the allowed budget of 1250 ns • Tests with new PS boards underway • Read-out path in full swing • Future Plan • Test-beam at CERN • Integration also to higher level systems → full chain to LVL1 Central Trigger Processor and to DAQ system.

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