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EXECUTION UNIT

INSTRUCTION PIPELINE. BUS INTERFACE UNIT. EXECUTION UNIT. SYSTEM BUS. BUS INTERFACE UNIT(BIU). EXECUTION UNIT(EU). SEGMENT REGISTERS. GENERAL REGISTERS. INSTRUCTION POINTER. MULTIPLEXED BUS. ADDRESS GENERATION & BUS CONTROL. OPERANDS. INSTRUCTION QUEUE. ALU.

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EXECUTION UNIT

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  1. INSTRUCTION PIPELINE BUS INTERFACE UNIT EXECUTION UNIT SYSTEM BUS

  2. BUS INTERFACE UNIT(BIU) EXECUTION UNIT(EU) SEGMENT REGISTERS GENERAL REGISTERS INSTRUCTION POINTER MULTIPLEXED BUS ADDRESS GENERATION & BUS CONTROL OPERANDS INSTRUCTION QUEUE ALU INTERNAL ARCHITECTURE OF 8088/8086 MICRPPROCESSOR FLAGS

  3. PIPELINED ARCHITECTURE EXECUTE FIRST INST EXECUTE SECOND INST EXECUTE THIRD INST EU FETCH FIRST INST FETCH SECOND INST WRITE RESULT FETCH THIRD INST READ OPERAND FETCH FOURTH INST BIU

  4. SOFTWARE MODEL OF 8088/8086 MPU OOOOOH EXTERNAL MEMORY ADDRESS SPACE 8088/8086 MPU IP CODE SEGMENT (64 K BYTES) CS 0000H INPUT/OUTPUT ADDRESS SPACE DS DATA SEGMENT (64K BYTES) SS ES AH AL BH BL CH CL STACK SEGMENT (64 K BYTES) DH DL SP BP SI FFFFH DI EXRA SEGMENT (64 K BYTES) SR FFFFFH

  5. PHYSICAL MEMORY ALIGNED WORDS ADDRESS BYTE 8 00008H BYTE 7 00007H WORD 6 BYTE 6 00006H WORD 5 BYTE 5 00005H WORD 4 BYTE 4 00004H BYTE 3 00003H WORD 2 BYTE 2 0002H WORD 1 BYTE 1 00001H WORD 0 BYTE 0 00000H MISALIGNED WORDS

  6. PHYSICAL MEMORY ALIGNED DOUBLE WORDS ADDRESS BYTE 8 00008H BYTE 7 00007H DOUBLE WORD 5 BYTE 6 00006H DOUBLE WORD 4 BYTE 5 00005H DOUBLE WORD 3 BYTE 4 00004H DOUBLE WORD 2 BYTE 3 00003H DOUBLE WORD 1 BYTE 2 DOUBLE WORD 0 0002H BYTE 1 00001H BYTE 0 00000H MISALIGNED DOUBLE WORDS

  7. H L 15 8 7 0 AX ACCUMULATOR AH AL BX BASE BH BL CX COUNT CH CL DX DATA DH DL

  8. Register Operations AX WORLD MULTIPLY, WORD DIVIDE, WORD I/O AL BYTE MULTIPLY, BYTE DIVIDE, I/O TRANSLATE, DECIMAL ARITHMETIC AH BYTE MULTIPLY, BYTE DIVIDE BX TRANSLATE CX STRING OPERATIONS, LOOPS CL VARIABLE SHIFT AND ROTATE DX WORLD MULTIPLY, WORD DIVIDE, INDIRECT I/O 0 15 SP STACK POINTER BP BASE POINTER SI SOURCE INDEX DI DESTINATION INDEX

  9. TYPE OF REFERENCE DEFAULT ALTERNATE OFFSET SEGMENT SEGMENT INSTRUCTION FETCH CS NONE IP STACK OPERATION SS NONE SP DATA DS CS, ES OR SS VARIOUS STRING SOURCE DS CS, ES OR SS SI STRING DESTINATION ES NONE DI BP USED AS A BASE REGISTER SS CS, ES OR SS VARIOUS DEFAUT & ALTERNATE ADDRESS SOURCES

  10. TF DF IF OF SF ZF AF CF PF CARRY PARITY AUXIIARY FLAG ZERO SIGN OVERFLOW INTERRUPT ENABLE DIRECTION TRAP STATUS OR FLAG REGISTER

  11. FLAG MEANING SET RESET OF OVERFLOW OV (OVERFLOW) NV (NO OVERFLOW) DF DIRECTION DN (DOWN) UP (UP) IF INTERUPT EI (ENABLE INT) DI (DISABLE INT) SF SIGN NG (NEGATIVE) PL (PLUS) ZF ZERO ZR (ZERO) NZ (NOT ZERO) AF AUXILIARY FLAG AC (AUX FLAG) NA (NO AUX FLAG) PF PARITY PE (EVEN PARITY) PO (ODD PARITY) CF CARRY CY (CARRY) NC (NO CARRY) TF TRAP SINGLE-STEP MODE

  12. 0 15 OFFSET VALUE OFFSET 0 15 SEGMENT REGISTER 0 0 0 0 SEGMENT ADDRESS ADDER 19 0 20 BIT PHYSICAL MEMORY ADDRESS GENERATING A PHYSICAL ADDRESS

  13. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 8B MOV AX,BX 8088 MPU 01001 C3 01002 XX NEXT INSTRUCTION IP 0000 CS 0100 DS SS ES XXXX AX ABCD BX CX DX SP BP FIG. 1.1 (a) REGISTER ADDRESSING MODEINSTRUCTION BEFORE FETCH AND EXECUTION SI DI

  14. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 8B MOV AX,BX 8088 MPU 01001 C3 01002 XX NEXT INSTRUCTION IP 0002 CS 0100 DS SS ES ABCD AX ABCD BX CX DX SP BP FIG. 1.1 (b) REGISTER ADDRESSING MODEINSTRUCTION AFTER EXECUTION SI DI

  15. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 B0 MOV AL,15H 8088 MPU 01001 15 01002 XX NEXT INSTRUCTION IP 0000 01003 XX CS 0100 DS SS ES XX AX BX CX DX SP BP FIG. 1.2 (a) IMMEDIATE ADDRESSING MODEINSTRUCTION BEFORE FETCH AND EXECUTION SI DI

  16. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 B0 MOV AL,15H 8088 MPU 01001 15 01002 XX NEXT INSTRUCTION IP 0002 01003 XX CS 0100 DS SS ES 15 AX BX CX DX SP BP FIG. 1.2 (b) IMMEDIATE ADDRESSING MODEINSTRUCTION AFTER EXECUTION SI DI

  17. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 8B MOV CX, [1234H] 8088 MPU 01001 0E 01002 34 IP 0000 01003 12 CS 01004 XX NEXT INSTRUCTION 0100 DS 0200 SS 02000 XX ES 02001 XX . . AX . BX 03234 ED xxxx CX SOURCE OPERAND 03225 BE DX SP BP FIG. 1.4 (a) DIRECT ADDRESSING MODEINSTRUCTION BEFORE FETCH AND EXECUTION SI DI

  18. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 8B MOV CX, [1234H] 8088 MPU 01001 0E 01002 34 IP 0004 01003 12 CS 01004 XX NEXT INSTRUCTION 0100 DS 0200 SS 02000 XX ES 02001 XX . . AX . BX 03234 ED BEED CX SOURCE OPERAND 03225 BE DX SP BP FIG. 1.4 (b) DIRECT ADDRESSING MODEINSTRUCTION AFTER EXECUTION SI DI

  19. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 8B MOV AX, [SI] 8088 MPU 01001 04 01002 XX NEXT INSTRUCTION IP 0000 CS 0100 DS 0200 SS 02000 XX ES 02001 XX . . XXXX AX . BX 03234 ED CX SOURCE OPERAND 03235 BE DX SP FIG. 1.5 (a) REGISTER INDIRECT ADDRESSING MODE INSTRUCTION BEFORE FETCH & EXECUTION BP 1234 SI DI

  20. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 8B MOV AX, [SI] 8088 MPU 01001 04 01002 XX NEXT INSTRUCTION IP 0002 CS 0100 DS 0200 SS 02000 XX ES 02001 XX . . BEED AX . BX 03234 ED CX 03235 BE DX SP FIG. 1.5 (b) REGISTER INDIRECT ADDRESSING MODE INSTRUCTION AFTER EXECUTION BP 1234 SI DI

  21. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 88 MOV [BX]+1234H,AL 8088 MPU 01001 87 01002 34 NEXT INSTRUCTION IP 0000 01003 12 CS 01004 XX 0100 DS 0200 SS 02000 XX ES 02001 XX . . BE ED AX . 1000 BX 04234 XX CX 04235 XX DX SP INSTRUCTION USING DIRECT BASE POINTER ADDRESSING MODE BEFORE FETCH AND EXECUTION BP SI DI

  22. MEMORY CONTENTS ADDRESS INSTRUCTION 01000 88 MOV [BX]+1234H,AL 8088 MPU 01001 87 01002 34 NEXT INSTRUCTION IP 0000 01003 12 CS 01004 XX 0100 DS 0200 SS 02000 XX ES 02001 XX . . BE ED AX . 1000 BX 04234 ED CX 04235 XX DX SP INSTRUCTION USING DIRECT BASE POINTER ADDRESSING MODE AFTER EXECUTION BP SI DI

  23. BYTE 2 BYTE 3 BYTE 4 BYTE 1 BYTE 5 BYTE 6 LOW DISP/DATA HIGH DISP/DATA HIGH DATA LOW DATA MOD REG R/M OPCODE D W DATA SIZE BIT W=1 WORD OPERATION W=0 BYTE OPERATION DIRECTION BIT D=1 FOR DESTINATION OPERAND D=0 FOR SOURCE OPERAND

  24. CODE 00 01 10 11 EXPLANATION MEMORY MODE, NO DISPLACEMENT MEMORY MODE, 8-BIT DISPLACEMENT FOLLOWS MEMORY MODE, 16-BIT DISPLACEMENT FOLLOWS REGISTER MODE. (NO DISPLACEMENT) REG 000 001 010 011 100 101 110 111 W=0 AL CL DL BL AH CH DH BH W=1 AX CX DX BX SP BP SI DI MODE (MOD) FIELD ENCODING REGISTER (REG) FIELD CODING MODE=11 EFFECTIVE ADDRESS CALCULATION R/M 000 001 010 011 100 101 110 111 W=0 AL CL DL BL AH CH DH BH W=1 AX CX DX BX SP BP SI DI R/M 000 001 010 011 100 101 110 111 MOD=00 (BX)+(SI) (BX)+(DI) (BP)+(SI) (BP)+(DI) (SI) (DI) DIRECT ADDRESS (BX) MOD=01 (BX)+(SI)+D8 (BX)+(DI)+D8 (BP)+(SI)+D8 (BP)+(DI)+D8 (SI) )+D8 (DI) )+D8 (BP)+D8 (BX)+D8 MOD=10 (BX)+(SI)+D16 (BX)+(DI)+D16 (BP)+(SI)+D16 (BP)+(DI)+D16 (SI)+D16 (DI)+D16 (BP)+D16 (BX)+D16 REGISTER/MEMORY (R/M) FIELD ENCODING

  25. REGISTER ES CS SS DS SR 00 01 10 11 SEGMENT REGISTER CODES FIELD S V Z VALUE 0 1 0 1 0 1 FUNCTION NO SIGN EXTENSION SIGN EXTEND 8-BIT IMMEDIATE DATA TO 16-BITS IF W=1 SHIFT/ ROTATE COUNT IS ONE SHIFT/ ROTATE COUNT IS SPECIFIED IN CL REGISTER REPEAT/LOOP WHILE ZERO FLAG IS CLEAR REPEAT/LOOP WHILE ZERO FLAG IS SET ADDITIONAL 1-BIT FIELDS & THEIR FUNCTIONS

  26. Symbol Register AX Accumulator Register BX Base Register CX Count Register DX Data Register SI Source Index Register DI Destination Index Register SP Stack Pointer Register BP Base Pointer Register CS Code Segment Register DS Data Segment Register SS Stack Segment Register ES Extra Segment Register F Flag SRegister IP Instruction Pointer Register mnemonics for the R command

  27. Addition ADD Add byte or word ADC Add byte or word with carry INC Increment byte or word by 1 AAA ASCII adjust for addition DAA Decimal adjust for addition Subtraction SUB Subtract byte or word SBB Subtract byte or word with borrow DEC Decrement byte or word by 1 NEG Negate byte or word AAS ASCII adjust for subtraction DAS Decimal adjust for subtraction Multiplication MUL Multiply byte or word unsigned IMUL Integer multiply byte or word AAM ASCII adjust for multiply Division DIV Divide byte or word unsigned IDIV Integer divide byte or word unsigned AAD ASCII adjust for division CBW Convert byte to word CWD Convert word to double word Arithmetic Instructions

  28. Mnemonics Meaning Format Operation Flags affected MOV Move MOV D,S (S) (D) None MOV data transfer instruction Destination Source Memory Accumulator Accumulator Memory Register Register Register Memory Memory Register Register Immediate Memory Immediate Seg-reg Reg16 Seg-reg Mem16 Reg16 Seg-reg Memory Seg-reg Allowed Operands

  29. Mnemonics Meaning Format Operation Flags affected Xlate Translate XLAT ((AL)+(BX)+(DS)0 (AL) None Xlate data transfer instruction

  30. Mnemonics Meaning Format Operation Flags affected XCHG Exchange XCHG D,S (D) (S) None Exchange data transfer instruction Destination Source Accumulator Reg16 Memory Register Register Register Register Memory Allowed Operands

  31. IMMEDIATE TO REGISTER/MEMORY 1 1 0 0 0 1 1 W MOD 0 0 0 R/M DISP-LO DISP-HI DATA DATA IF W=1 IMMEDIATE TO REGISTER 1 0 1 1 W REG DATA DATA IF W=1 MEMORY TO ACCUMULATOR 1 0 1 0 0 0 W ADDR-LO ADDR-HI REGISTER /MEMORY TO SEGMENT REG DISP-HI 1 0 0 0 1 1 1 0 MOD 0 SR R/M DISP-LO SEGMENT REG TO REGISTER/ MEMORY DISP-HI 1 0 0 0 1 1 0 0 MOD 0 SR R/M DISP-LO MOVE COMMANDS

  32. ADDRESS CHARACTER Memory (EBCDIC) 00 . . F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 7A 4C 7E 6E 6F 7C C1 C2 C3 C4 C5 03100 NULL 0300 DS 03110 0 1 2 3 4 5 6 7 8 9 : ; < = ? @ A B C D E 0100 BX AX XX3F BEFORE EXECUTION XX6F AX AFTER EXECUTION 0313F 03141 ASCII to EBCDIC Conversion operation (Translate Instruction)

  33. Mnemonic Meaning Format Operation Flags affected LEA Load effective address LEA Reg16,EA EA (Reg16) None LDS Load register and DS LDS Reg16,Mem32 (Mem32 ) (Reg16) None (Mem32+2) (DS) LES Load register and ES LES Reg16,Mem32 (Mem32) (Reg16) None (Mem32+2) (ES) LEA, LDS & LES Instructions

  34. MEMORY CONTENTS ADDRESS INSTRUCTION 11100 C5 LDS SI , [200H] 8088 MPU 11101 36 11102 00 IP 0100 11103 02 CS 11104 XX NEXT INSTRUCTION 1100 DS 1200 SS 12000 XX ES 12001 XX . . AX . BX 12200 20 CX 12201 00 DX 12202 00 12203 13 SP BP FIG. LDS INSTRUCTION BEFORE FETCH AND EXECUTION XXXX SI DI

  35. MEMORY CONTENTS ADDRESS INSTRUCTION 11100 C5 LDS SI , [200H] 8088 MPU 11101 36 11102 00 IP 0104 11103 02 CS 11104 XX NEXT INSTRUCTION 1100 DS 1300 SS 12000 XX ES 12001 XX . . AX . BX 12200 20 CX 12201 00 DX 12202 00 12203 13 SP . BP 13000 XX 0020 SI 13001 XX DI FIG. LDS INSTRUCTION AFTER EXECUTION

  36. REG/MEM WITH REG TO EITHER 0 0 0 0 0 0 D W MOD REG R/M DISP-LO DISP-LO 1 0 0 0 0 0 D W MOD REG R/M DISP-LO DISP-LO DATA DATA IF W=1 IMMEDIATE TO REG/MEM IMMEDIATE TO ACCUMULATOR 0 0 0 0 0 1 0 W DATA DATA IF W=1 ADD INSTRUCTIONS

  37. Compare Instruction Mnemonic Meaning Format Operation Flags affected CMP Compare CMP D, S (D) (S) is used OF, SF, ZF, AF, PF, CF in setting or resetting the flags Destination Source Register Register Register Memory Memory Register Register Immediate Memory Immediate Accumulator Immediate Allowed Operand

  38. Unconditional jump Instruction Mnemonic Meaning Format Operation Flags affected jMP Unconditional JMP Operand Jump is initiated None jump to the address specified by the operand Operands Short – Label Near – Label Far – Label Memptr 16 Regptr 16 Memptr 32 Allowed Operand

  39. Conditional jump Instruction Mnemonic Meaning Format Operation Flags affected jcc Conditional Jcc Operand If the specified condition cc None jump is true the jump to the address specified by the operand is initiated; otherwise the next instruction is executed

  40. Subroutine call Instruction Mnemonic Meaning Format Operation Flags affected CALL Subroutine call CALL Operand Execution continues from None address of the subroutine specified by the operand. Information required to return back to the main program such as IP and CS are saved on the stack Operand Near-proc Far-proc Memptr16 Regptr16 Memptr32 Allowed Operand

  41. Mnemonic Meaning Condition JA Above CF=0 and ZF=0 JAE Above or equal CF=0 JB below CF=1 JBE Below or equal CF=1 or ZF=1 JC Carry CF=1 JCXZ CX reg is zero (CF or ZF)=0 JE Equal ZF=1 JG greater ZF=0 & SF=OF JGE Greater or equal SF=OF JL Less (SF xor OF)=1 JLE Less or equal ((S Fxor OF)orZF=1 JNA not above CF=1 or ZF=1 JNAE not above nor equal CF=1 JNB not below CF=0 JNBE not above nor equal CF=0 & ZF=0 JNC not carry CF=0 JNE not equal ZF=0 JNG not greater ((SF xor OF)orZF=1 JNG not greater or equal (SF xor OF)=1 JNL not less SF=OF JNLE not less or equal ZF=0 & SF=OF JNO not overflow OF=0 JNP not parity PF=0 JNS not sign SF=0 JNZ not zero ZF=0 JO overflow OF=1 JP parity PF=1 JPE parity even PF=1 JPO parity odd PF=0 JS Sign SF=1 JZ zero ZF=1 Conditional Jump Instructions

  42. Main Program . . . Call Subroutine A Next instruction . . . . . Subroutine A First instruction Call Subroutine A Next Instruction . . . . Return Subroutine concept

  43. Addition Instructions Mnemonic Meaning Format Operation Flags affected ADD Addition ADD D, S (S)+(D) (D) OF, SF, ZF, AF, PF, CF Carry (CF) ADC Add with carry ADC D, S (S)+(D) + (CF) (D) OF, SF, ZF, AF, PF, CF Carry (CF) INC Increment by 1 INC D (D) + 1 (D) OF, SF, ZF, AF, PF, AAA ASCII adjust AAA AF, CF for addition OF, SF, ZF, PF undefined DAA Decimal adjust DAA SF, ZF, AF, PF, CF for addition OF, Undefined Destination Source Register Register Register Memory Memory Register Register Immediate Memory Immediate Accumulator Immediate Destination Reg16 Reg8 Memory Allowed Operand For Increment Allowed Operand For Addition

  44. Subtraction Instructions Mnemonic Meaning Format Operation Flags affected SUB Subtract SUB D, S (D)-(S) (D) OF, SF, ZF, AF, PF, CF Borrow (CF) SBB Subtract with ADC D, S (D) - (S) - (CF) (D) OF, SF, ZF, AF, PF, CF Borrow DEC Decrement by 1 INC D (D) - 1 (D) OF, SF, ZF, AF, PF, NEG Negate NEG D 0-(D) (D) OF SF, ZF, AF, PF, CF 1 (CF) DAS Decimal adjust DAS SF, ZF, AF, PF, CF for subtraction OF, Undefined AAS ASCII adjust AAS AF, CF for subtraction OF, SF, ZF, PF undefined Destination Source Register Register Register Memory Memory Register Register Immediate Memory Immediate Accumulator Immediate Destination Reg16 Reg8 Memory Destination Register Memory Allowed Operand for NEG instruction Allowed Operand For Decrement Instruction Allowed Operand For Subtraction Instruction

  45. Multiplication & Division Instructions Mnemonic Meaning Format Operation Flags affected MUL Multiply MUL S (AL) . (S8) (AX) OF, CF (unsigned) (AX . (S16) (DX),(AX) SF, ZF, AF, PF undefined DIV Division DIV S (1) Q((AX)/(S8) (AL) OF, SF, ZF, AF, PF, CF (unsigned) R((AX)/(S8) (AH) undefined (2) Q((DX,AX)/(S16) (AX) R((DX,AX)/(S16) (DX If Q is FFH in case (1) or FFFFH in case (2), then type 0 interrupt occurs IMUL Integer Multiply IMUL S (AL) . (S8) (AX) OF, SF, ZF, AF, PF,CF (signed) (AX) . (S16) (DX),(AX) undefined IDIV Integer divide IDIV S(1) Q((AX)/(S8) (AL) (signed) R((AX)/(S8) (AH) (2) Q((DX,AX)/(S16) (AX) R((DX,AX)/(S16) (DX If Q is positive and exceeds 7FFFH or if Q is negative and becomes less than 8001H then type 0 interrupt occurs AAM Adjust AL for AAM Q((AL)/10) (AH) SF, ZF, , PF, multiplication R((AL)/10) (AL) OF, AF, CF Undefined AAD Adjust AX for AAD (AH).10+(AL) (AL) SF, ZF, PF division OF, AF, CF undefined CBW Convert byte CBW (MSB of AL) (All bits of AH) None to word CWD Convert word to CWD (MSB of AX) (All bits of DX) None double word

  46. MOV AX,2000H ; LOAD AX REGISTER MOV DS,AX ; LOAD DATA SEGMENT ADDRESS MOV SI,100H ; LOAD SOURCE BLOCK POINTER MOV DI,120H ; LOAD DESTINATION BLOCK POINTER MOV CX,10H ; LOAD REPEAT COUNTER MOV AH,[SI] ; MOVE SOURCE BLOCK ELEMENT TO AH MOV [DI],AH ; MOVE AH TO DESTINATION BLOCK INC SI ; INCREMENT SOURCE BLOCK POINTER INC DI ; INCREMENT DESTINATION BLOCK POINTER DEC CX ; DECREMENT REPEAT COUNTER JNZ NXTPT ; JUMP TO NXTPT IF CX NOT EQUAL TO ZERO NOP ; NO OPERATION NXTPT:

  47. Part 1 JMP AA Part 1 Jcc AA Conditional Jump Instruction Unconditional Jump Instruction Condition met Next instruction executed if condition not met No Part II XXXXXX Locations skipped due to jump Locations skipped due if jump taken Yes Part II AA XXXXXX Next Instruction executed AA XXXXXX Next instruction Executed if Condition met Part III Conditional jump Program sequence Unconditional jump Program sequence

  48. Flag Control Instructions Mnemonic Meaning Operation Flags affected LAHF Load AH from Flags (AH) (Flags) None SAHF Store AH into flags (Flags) (AH) SF, ZF, AF, PF, CF CLC Clear carry flag (CF) 0 CF STC Set carry flag (CF) 1 CF CMC Compliment carry flag (CF) (CF) CF CLI Clear Interrupt flag (IF) 0 IF STI Set Interrupt flag (IF) 1 IF SF = Sign flag ZF = Zero flag AF = Auxiliary flag PF = Parity flag CF = Carry flag

  49. Logic Instructions Mnemonic Meaning Format Operation Flags affected AND Logical AND AND D, S (S)+(D) (D) OF, SF, ZF, PF, CF AF undefined OR Logical ADC D, S (S)+(D) (D) OF, SF, ZF, AF, PF, CF Inclusive-OR AF undefined XOR Logical XOR D, S (S)+(D) (D) OF, SF, ZF, CF, PF Exclusive-OR AF undefined NOT Logical NOT NOT D (D)’ (D) None Destination Source Register Register Register Memory Memory Register Register Immediate Memory Immediate Accumulator Immediate Destination Register Memory Allowed Operand For NOT Instruction Allowed Operands for AND, OR, XOR Instruction

  50. Shift Instructions Mnemonic Meaning Format Operation Flags affected SAL/SHL Shift SAL/SHL D, Count Shift the (D) left by the number of OF, SF, ZF, PF, CF arithmetic bit positions equal to the count and left/shift fill the vacated bits positions OF undefined if count logical left on the right with zereos not equal to 1 SHR Shift SHR D, Count Shift the (D) right by the number of OF, SF, ZF, AF, PF, CF logical bit positions equal to count and AF undefined right fill the vacated bits positions OF undefined if count on the left with zereos not equal to1 SAR Shift SAR D, Count Shift the (D) right by the number of OF, SF, ZF, CF, PF arithmetic bit positions equal to count and AF undefined right fill the vacated bits positions on the left with the original most significant bit. Destination Count Register 1 Register CL Memory 1 Memory CL

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