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Unified Debug Environment for Adaptive Computing Systems

Unified Debug Environment for Adaptive Computing Systems. Brigham Young University Provo, UT September 13, 1999. Introduction and Motivation. Basic Premise. FPGAs bring something unique to the party. What is unique?. FPGAs are faster?. What is unique?. FPGAs are reprogrammable?. ASIC.

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Unified Debug Environment for Adaptive Computing Systems

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  1. Unified Debug Environment for Adaptive Computing Systems Brigham Young University Provo, UT September 13, 1999

  2. Introduction and Motivation

  3. Basic Premise FPGAs bring something unique to the party.

  4. What is unique? FPGAs are faster?

  5. What is unique? FPGAs are reprogrammable? ASIC

  6. What is unique? FPGAs are always available? FPGAs

  7. What is unique? FPGA Potential: Hardware development becomes software development.

  8. edit compile execute/debug Good News modify design synthesize download/verify FPGA development cycle is similar to software development cycle.

  9. Bad News place&route/ download scratch head synthesize modify design simulate/verify execute There are two development cycles!

  10. Issues 1000s of times slower... 1000s of times faster... simulate/verify execute/scratch head excellent visibility poor visibility Either approach is insufficient.

  11. Goal: One Efficient Cycle 1000s of times faster... execute/verify excellent visibility

  12. Main Issue Need to provide “software” visibility when debugging hardware.

  13. What is Software Debugging? • Debug prints. • Examine/watch variables. • Modify variables. • Single-step/multistep. • Breakpoints.

  14. Can’t I just use VHDL? • Simulation: Yes (but that was always the case). • Execution: No • Cannot control HW platform via VHDL. • Automatic downloading of bitstreams. • Patching the bitstream for debug “prints”. • Controlling the clock. • Accessing platform memory.

  15. Do I have to use JHDL? • NO! • EDIF can be translated to JHDL debug format. • All debugging tools operate using the debug format. • User-defined signal names will be generally available via the debugging tools.

  16. General Vision • FPGAs programmed and debugged similar to software. • Use general-purpose languages for programming. • Use software-like debugging techniques. • Provide EDIF-interchange for access via other tools.

  17. Project Overview

  18. Goal Create a productive environment for debug and development that exploits the unique features of ACS.

  19. Specifics • Unified access to simulation and execution. • Multitasking support for hardware execution. • Control of the platform from remote locations. • Automatic synthesis of debug circuitry. • Checkpointing of execution and simulation. • Support for external high-level tools.

  20. General Software Architecture

  21. Unified Simulation/Execution Simulator Simulate ATR X3 X4 ATR Circuit Description X1 X2 JHDL Library data Configure/ Execute X0 configure Simulator/Run-time API HW Manager ACS Platform

  22. ACS Platform Single-User Systems Who’s got the board? Who’s got the ?&?# board? Glad nobody needs the board.

  23. ACS Platform Hardware Multitasking Multitasking ACS Server

  24. Remote Access

  25. ACS Platform ACS Platform Remote Access Access ACS Hardware away from Laboratory ACS Platform ACS Platform Home Across Campus Across Hall

  26. ACS Platform ACS Platform Remote Access Centralize Maintenance and Support • It is expensive to outfit and support ACS technology • ACS technology can be fragile ACS Platform ACS Platform ACS Platform

  27. ACS Platform ACS Platform ACS Platform ACS Platform Remote Access Extend availability of ACS technology • Collaborate with large distributed development teams • Provide ACS hardware access to those without ACS capability Universities Public School Internet Access ACS Platform Industry

  28. ACS Platform ACS Platform Remote Access - Issues No standardized client architecture • User interfaces are unique (cannot export host display!) • Only simple protocols available (http, ftp, telnet, etc.) ACS Platform ACS Platform Windows NT Mac HP Workstation Sun Workstation Linux x86 Workstation

  29. ACS Platform ACS Platform Remote Access - Issues Network Bandwidth Limitations • Must limit the data needed for remote access/debug • Exporting user interface consumes excessive bandwidth v.34 ACS Platform ACS Platform LAN slip

  30. ACS Platform ACS Platform Remote Access - Issues Security/Safety • Must insure access to ACS hardware is restricted • Prevent inadvertent communication (download email to SLAAC board?) ACS Platform ACS Platform hacker

  31. Remote Access - Approach • Exploit platform independence of Java/JHDL • Create unique communication protocol • Limit ACS to client communication to essential control and data information • Add security layer to remote communication protocol • Provide same interface to ACS hardware without requiring login access to host machine

  32. ACS Platform Remote Access - Approach jhdl/browser ACS protocol security jvm (x86) ACS protocol jhdl/browser security ACS protocol ACS server security Hardware API jvm (mac) Hardware

  33. Debug Circuitry

  34. Debug Circuitry Synthesis ? • Simulation routinely used for debugging circuits • Greater visibility • More control over execution • Easy to use interfaces • Facilitate the use of hardware debugging by synthesizing custom circuits

  35. 16 D D Q Q Q Q Debug Circuitry Synthesis ?

  36. 16 D D Q Q Q Q Debug Circuitry Synthesis Additional Wires and I/O for Visibility 0 1 0

  37. 16 D D Q Q Q Q Debug Circuitry Synthesis Memory Buffers for Real-Time Data Capture Signal Buffer

  38. 16 D D Q Q Q Q Debug Circuitry Synthesis Logic Circuits for Hardware Breakpoints 0 Disable Clock

  39. 16 D D Q Q Q Q Event Counter Event Counter Debug Circuitry Synthesis Counters and Logic for System Profiling and Analysis 0

  40. Debug Circuitry Synthesis - Issues • Preserve speed/function of circuit • Debug circuitry may add delays • Circuitry may introduce logic errors • Remove debug circuits gracefully • Avoid place and route step • Limit turn around time for debug cycle • May not be possible with some technologies • Xilinx-Jbits (Guccione)

  41. Debug Circuitry Synthesis -Approach • Define API for specifying debugging needs • Develop platform independent synthesis tools • Create platform specific debugging libraries • Optimized state machines • Clock controllers • Memory buffers and counters

  42. Checkpointing Complete capture & restoration of simulation/execution state

  43. Watch different signals... Cycle 347K Cycle 100K Cycle 200K Cycle 300K Cycle 300K Cycle 200K Oops! Checkpoint store Checkpoint store Checkpoint store Checkpoint store Checkpoint store Checkpointing Simulate/execute from any saved point - repeat problem sections - continue tomorrow

  44. ACS Platform ACS Platform Simulation ACS Execution Checkpoint store Checkpoint store Checkpointing Mix simulation & execution ACS Platform Simulation ACS Execution or

  45. ACS Platform Checkpoint store Checkpointing Support for multitasking

  46. State capture Device issues flip flops LUT contents on-chip RAM’s Platform issues memories fifos control registers Hardware support for? Checkpointing Issues

  47. State capture State representation Custom format? Common format? Communication with other tools? Checkpointing Issues

  48. State capture State representation State storage Local vs. remote speed of access Hardware support for? Checkpointing Issues

  49. State capture State representation State storage State restoration Similar to capture device issues platform issues Hardware support for? Checkpointing Issues

  50. Checkpointing Concerns • Device support for • Xilinx, Altera, CSRC • Platform support for • Wild*, SLAAC1, CSRC, Altera platforms • Proprietary issues • need for open systems

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