332:578 Deep Submicron VLSI Design Lecture 27 Emerging Nanotechnology Devices

1. 332:578 Deep SubmicronVLSI DesignLecture 27Emerging Nanotechnology Devices Tezaswi Raja – Trans-Meta Corp. Prof. Vishwani Agrawal – Auburn U. Prof. Michael Bushnell – Rutgers U. Deep Submicron VLSI Des. Lec. 27

2. Outline • Introduction • Nano scale MOSFET • Carbon Nanotube FETs • Solid State Quantum Devices • Molecular Electronics • Challenges and current state of the art • Conclusions Deep Submicron VLSI Des. Lec. 27

3. Introduction • Feature sizes nearing the physical limits • Fabrication process reaches limits • Power consumption – a major concern • Quantum effects need to be accounted for • Solution? Nanotechnology • We present an inside view behind the hype into various devices and also to some open problems of research that it has created. Deep Submicron VLSI Des. Lec. 27

4. CNFETs Molecular RTD Molecules in Solution Quantum Dots Self assembled CNT using DNA DNA self assembly Molecular orientations as Bits DNA strands as Bits CNT arrays SETs What Is Nanotechnology? • Switching devices in the range of nanometers define nanotechnology • Is it enough only to make switches? • Memory devices? • Can we fabricate these devices any easier? Emerging Nanotechnology Vectors Emerging Nanotechnology Solutions Logic (Our Focus) Nano CMOS Memory Fabrication Deep Submicron VLSI Des. Lec. 27

5. Classification of Computing Solutions Solid State Devices Molecular Devices CMOS Devices Quantum Devices Nano CMOS CNFETs Quantum Dots RTDs SETs Quantum Electromechanical Photoactive Electrochemical Deep Submicron VLSI Des. Lec. 27

6. Nano Scale MOSFET Photo Courtesy: Fujitsu Labs • Metal Oxide Semiconductor Field Effect Transistor • Three terminal device • Source, Gate and Drain • Vg determines the conduction from Source to Drain • Half thickness of the gate is called “Feature size λ” • Current feature sizes in production – 90nm (Intel Pentium 5) • Demonstrated feature sizes down to 20nm (IBM) Deep Submicron VLSI Des. Lec. 27

7. Challenges and Summary Ref: Taur et al. Ref: Taur et al. • High Electric Fields • Power supply vs. Threshold Voltage • Heat Dissipation • Interconnect Delays • Vanishing Bulk Properties • Shrinkage of Gate Oxide layer • Summary • Too many problems to continue miniaturization as physical limits approach • Solutions proposed are short term • Open Problems and Initiatives • Improve Lithographic precision (eBeam) • Explore new materials (GaAs, SiGe, etc.) • As a long term goal explore new devices Ref: Taur et al. Deep Submicron VLSI Des. Lec. 27

8. Outline • Introduction • Nano scale MOSFET • Carbon Nanotube FETs • Solid State Quantum Devices • Molecular Electronics • Challenges and current state of the art • Conclusions Deep Submicron VLSI Des. Lec. 27

9. Carbon Nano-tubes • Carbon nanotubes are long meshed wires of carbon • IBM leading the research with longest tubes up-to 1mm long and a few nanometers thick Deep Submicron VLSI Des. Lec. 27

10. Electrical Conducting Properties • Carbon nanotubes can be metallic or semiconducting depending on their chirality • Chiral Vector C is defined as the vector from one open end of the tube to the other after it is rolled. • If (n-m) is divisible by 3, the tube is metallic • If (n-m) is not divisible by 3, the tube is semi-conducting • Further classified into • Zig-Zag n = m = 0 • Armchair n = m • Chiral n != m C = n a1 + m a2 Deep Submicron VLSI Des. Lec. 27

11. Carbon Nanotube FETs Courtesy: IBM Courtesy: IBM Courtesy: IBM • CNT can be used as the conducting channel of a MOSFET • These new devices are very similar to the CMOS FETs and hence are being preferred in the industry • All CNFETs are pFETs by nature • nFETs can be made through • Annealing • Doping • Very low power current/power consumption • Typical Gain (reported by IBM) = 0.8 – 1.2 • Although tubes are 3nm thick CNFETs are still the size of the contacts around 20nm Deep Submicron VLSI Des. Lec. 27

12. A Note on Fabrication • Controlling the conductivity of the tubes (Constructive Destruction) • All tubes laid on the contact • Metallic tubes are destroyed • Controlling diameter of the tube • Start with MWNTs • Destroy the outer layers one by one until required diameter is reached. • Placing exactly at the required location • Yet to be demonstrated convincingly to exploit complete advantage using Lithography • Using DNA for self assembly • Attach CNT to a DNA strand • Coat the contacts with complementary DNA strands • After ligation both complementary strands of DNA merge with each other placing the CNT on the contacts • Demonstrated by Techion-Israel Inst. of Tech. very recently in Nov. ’2003 Courtesy: IBM Courtesy: IBM Deep Submicron VLSI Des. Lec. 27

13. Challenges and Summary • CNTs are flexible tubes that can be made conducting or semiconducting. • Nano-scale, strong and flexible • Challenges: • Multilevel interconnects not available • Chip density still limited to the density of contacts • Tube density not entirely exploited • Fabrication is still a stochastic process • Alternatives to Gold contacts need to be found • Signal restoration is still a problem • Open Problems and Initiatives • Fabrication using DNA for self assembly (Technion-Israel Institute of Technology Science, Nov. 2003) • Memory array of these tubes using junctions as bit storages (Lieber’s group at Harvard) • Using these arrays to make computing elements (DeHon’s group at Cal. Tech) • Fabricate field-programmable gate arrays (FPGAs) using CNFETs and scanning tunneling microscope (STM) (Avouris’ group at IBM) Deep Submicron VLSI Des. Lec. 27

14. Outline • Introduction • Nano scale MOSFET • Carbon Nanotube FETs • Solid State Quantum Devices • Molecular Electronics • Challenges and current state of the art • Conclusions Deep Submicron VLSI Des. Lec. 27

15. Solid State Quantum Devices Occupied Energy Levels Occupied Energy Levels Occupied Energy Levels Occupied Energy Levels Energy Energy Barrier Barrier Allowed Energy Levels • Using Quantum effects to build devices • Electrons confined on an island • Island can be created by using different band-gap devices in succession • Island has certain allowed energy levels • If allowed energy levels are filled then the device is in conduction • Degree of freedom (d.o.f.) specifies the type of device • Resonant Tunneling Diode (RTD) – 1 d.o.f • Single Electron Transistor – 2 d.o.f. • Quantum Dot – 0 d.o.f. • Blocking conduction due to unavailable energy levels is called Coulomb Blockade Allowed Energy Levels Distance Distance Source Island Drain Source Island Drain Deep Submicron VLSI Des. Lec. 27

16. Principle of Conduction Conduction Conduction Occupied Conduction Band Occupied Conduction Band • Conduction can occur by • Increasing Bias Voltage • Applying Gate Voltage Energy Energy Allowed Energy Levels Allowed Energy Levels Occupied Conduction Band Applied Gate bias Distance Source Island Drain Source Island Drain Deep Submicron VLSI Des. Lec. 27

17. Single Electron Transistors (SET) Source Cg Gate • Conductance occurs in spurts as energy levels are discrete • To go from conducting to non-conducting stage, it requires voltage sufficient for one electron to cross • This is achieved by applying gate bias enough for just one electron charge • Hence the name SET • Bias required for conduction is Coulomb Gap Voltage • Same device can act as pFET and nFET based on the barrier strengths • Applications: • Extra sensitive charge meters • CMOS style conducting devices Island Drain Deep Submicron VLSI Des. Lec. 27

18. Quantum Dots and Arrays Dot occupied by Electron Inter-dot Barriers • 3 dimensional island barrier • State determined by presence of electron and not by conduction • Quantum cell array (QCA) is a lattice of these cells with 2 electrons confined • Occupied electrons are furthest from each other due to repulsive forces Dot unoccupied Outer Barriers Courtesy: vortex.tn.tudelft.nl/ grkouwen/kouwen.html Deep Submicron VLSI Des. Lec. 27

19. Quantum Cellular Automata 1 1 • 2 states – “1” and “0” • Electrostatic interaction of nearby cells makes the bits flip • Input to the cell is by manipulating the Inter-dot barriers • Logic gates can be constructed as shown QCA Wire “1” “0” Stable 1 0 Unstable QCA Inverter Deep Submicron VLSI Des. Lec. 27

20. Challenges and Summary • Summary • Electrons confined on an island • Allowed energy levels are discrete and allow the device to fluctuate between conducting and non-conducting • SET – 2 dimensional device with gate bias control • QD – single dimensional device with electron presence as state • QCA – Arrays of QDs used for computing • Challenges: • Background Charge may offset states • Sensitivity of tunneling current to barrier width (lithographic accuracy) • Sensitivity to uniform barrier widths • Cryogenic operation • Open Problems: • Lithographic methods with guaranteed accuracy • Self Assembly of systems • Background charge elimination • Synthesis and verification techniques for these architectures • Testing of these devices as stuck-at models may be inadequate Deep Submicron VLSI Des. Lec. 27

21. Outline • Introduction • Nano scale MOSFET • Carbon Nanotube FETs • Solid State Quantum Devices • Molecular Electronics • Challenges and current state of the art • Conclusions Deep Submicron VLSI Des. Lec. 27

22. Molecular Electronics • Incentives • Molecules are nano-scale • Self assembly is achievable • Very low-power operation • Highly uniform devices • Quantum effect Devices • Building quantum wells using molecules • Electromechanical devices • Using mechanical switching of atoms or molecules • Electrochemical devices • Chemical interactions to change shape or orientation • Photoactive devices • Light frequency changes shape and orientation Deep Submicron VLSI Des. Lec. 27

23. Molecular Electronics • Mechano-synthesis • Molecules aligned using a Scanning Tunneling Microscope (STM) • Fabrication done molecule by molecule using STM tip • Chemo-synthesis • Molecules aligned in place by chemical interactions • Self assembly • Parallel fabrication Deep Submicron VLSI Des. Lec. 27

24. Challenges and Summary • Summary • Parallel self assembly • Very regular structures • Many alternatives proposed but inherent problems • Very low energy operation • Challenges • Signal restoration and gain • Finding non-interacting chemicals • Chemical reactions stochastic with by-products • Very slow operating speeds • Open problems • Self assembling of devices • Increased speed of operation • Guaranteed switching of molecules (HP- UCLA devices) • Simulation models and CAD Deep Submicron VLSI Des. Lec. 27