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PPT-20314797

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  1. AE1SYS-CWP2-20314797 YUCHAN KO

  2. Table of content • x86 ARCHITECTURE • x86 Registers • x86 Instruction Set • Memory Management and Protection • 2. MULTICYCLE PROCESSOR • Multicycle Datapath • Multicycle Control • Performance Analysis • 3. PIPELINED PROCESSOR • Pipelined Datapath • Pipelined Control • Hazards and Their Resolution (Part 2)

  3. x86 ARCHITECTURE

  4. X86 ARCHITECTURE • ISAs based on the “Intel 8086" • Complex Instruction Set Computing (CISC) • Used in almost all computers • x86 is more complex but it can optimize in performance

  5. X86 REGISTERS Storage x86 Instruction Set OPERATIONS THAT CAN PERFORM Arithmetic, logic, control, and data transfer Memory Management and Protection How programs access memory, ensuring safety and efficiency

  6. Multicycle Processor

  7. MULTICYCLE PROCESSOR • Breaks instructions into smaller steps, allowing for a more efficient use of resources. • Microarchitecture level • Single-cycle takes long and less efficient

  8. MULTICYCLE DATAPATH THE PATH THAT THE DATA TAKES THROUGH A PROCESSOR Multicycle Control LOGIC THAT CONTROLS THE SEQUENCE OF OPERATIONS Performance Analysis A TECHNIQUE FOR EVALUATING THE EFFICIENCY AND SPEED OF MULTICYCLE PROCESSOR

  9. Pipelined Processor

  10. PIPELINED PROCESSOR • Advanced CPU designs to increase instruction throughput - the number of instructions that can be executed in a unit of time • Pipeline improves CPU performance • Operates at the microarchitecture level

  11. PIPELINED DATAPATH COMPONENT OF PROCESSORS THAT ALLOW MAKE OVERLAPPING INSTRUCTION EXECUTION VIABLE Pipelined Control LOGIC REQUIRED TO MANAGE AND SYNCHRONIZE INSTRUCTIONS Hazards and Their Resolution THE CHALLENGES FOR USING PIPELINE

  12. Hazards and Their Resolution in Pipelined Processors

  13. MORE INFORMATION.. • As said earlier.. • Instructions are executed in an overlapping manner • Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory Access (MEM), and Write Back (WB) • But this approach introduces hazards..

  14. HAZARDS • Data Hazards • Instructions that are close together and need access to the same data. Making it unable for smooth execution. • Read After Write (RAW) • Write After Read (WAR) • Write After Write (WAW) • Control Hazards • Do I fetch the next sequential instruction or a branch destination? • This wastes too much time • Structural Hazards • When hardware resources are insufficient to execute all concurrent instructions

  15. RESOLUTIONS FOR • structural hazards • Resource duplication • Duplicating resources to prevent conflict • pipeline interlocking • Stalls until the hazard is cleared • control hazards • branch prediction • Predicting the outcome of a branch • delayed branching • Allow the processor to reorder instructions so that it is always executed • data hazards • Forwarding/By-passing • Feeding the output of an ALU directly into another stage of the pipeline • Stalling • Inserting 'no operation' (NOP)

  16. LATEST INDUSTRY DEVELOPMENTS Adaptive or Dynamic Branch Prediction techniques Algorithm used to predict the direction of branches ex) Tournament Predictor / Branch Prediction Speculative Execution Processors that execute instruction ahead of time or rolling back if it is incorrect

  17. Thanks for Listening!

  18. REFERENCES • Information: • Harris, D. M., & Harris, S. L. (2012). Digital Design and computer architecture (2nd ed.). Morgan Kaufmann. Chapter 6 and 7. • Images: • Harris, D. M., & Harris, S. L. (2012). Digital Design and computer architecture (2nd ed.). Morgan Kaufmann. Chapter 6 and 7. • Wikipedia. (2016). Intel C8086. https://en.wikipedia.org/wiki/Intel_8086#/media/File:Intel_C8086.jpg • Branch Prediction. (2016). The Beard Sage. http://thebeardsage.com/branch-prediction/.

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