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Chapter 5 68000’s Instruction Set

Chapter 5 68000’s Instruction Set. Data movement: MOVE, LEA, etc. Arithmetic operations: ADD, SUB, MULU, DIVS, etc. Logical, shift, and bit operations: ASL, ASR, LSL, LSR, BTST, etc. Testing, conditional and unconditional branch instructions: Bcc, BRA, JMP, etc. Data Movement.

JasminFlorian
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Chapter 5 68000’s Instruction Set

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  1. Chapter 5 68000’s Instruction Set Data movement: MOVE, LEA, etc. Arithmetic operations: ADD, SUB, MULU, DIVS, etc. Logical, shift, and bit operations: ASL, ASR, LSL, LSR, BTST, etc. Testing, conditional and unconditional branch instructions: Bcc, BRA, JMP, etc.

  2. Data Movement MOVE Copy an 8-, 16-, or 32-bit value from memory or register to memory or register MOVE.B #$80,D0 MOVE to CCR To move a data to the condition code register MOVE #%00001,CCR

  3. MOVEQ Sign-extend an 8-bit value to 32 bits and copy to a data register MOVEQ #-3,D2 ;[D2]  FFFFFFFD Why is it “quicker” than MOVE.L? Machine codeAssembly code * MOVE.L and MOVEQ 203CFFFFFFFD MOVE.L #-3,D0 ;[D0]  3 70FD MOVEQ #-3,D0

  4. MOVEA Copy a sign-extended 32-bit value to address register MOVEA.W #$8C00,A0 ;[A0]  FFFF8C00 Compare to MOVEA.L #$8C00,A0 ;[A0]  ? Machine codeAssembly code * MOVEA.L and MOVEA.W 207CFFFFFFFD MOVEA.L #-3,A0 ;[A0] <- $FFFFFFFD 307CFFFD MOVEA.W #-3,A0

  5. Why do we need S bit? T S I2 I1 I0 X N Z V C Interrupt Mask CCR Op Mode Status Byte MOVE to/from SR Move to SR is privileged instruction. In SR, S=0 means operation under user mode; S=1 means operation under supervisor mode T: Trace, T = 1  diagnostic Mode Copy data to/from status register. MOVE SR,D3

  6. 4000 4000 4004 4004 D0 4008 4008 D1 400C 400C D2 4010 4010 D3 4014 4014 D4 4018 4018 A0 401C 401C A1 4020 4020 A2 4024 4024 4024 4008 MOVEM Transfer the contents of a group of registers to consecutive memory locations MOVEM.L D0-D4/A0-A2,-(A7) ... MOVEM.L (A7)+,D0-D4/A0-A2 Why is it useful?

  7. REG Define register list. ORG $400 SAVE_ALL: REG A0-A6/D0-D7 SAVE_FEW: REG A0-A1/A4-A5/D0-D2/D7 … PROCA: MOVEM.L SAVE_ALL,-(A7) … MOVEM.L (A7)+,SAVE_ALL RTS … PROCB: MOVEM.L SAVE_FEW,-(A7) … MOVEM.L (A7)+,SAVE_FEW RTS END $400

  8. Exchange the entire 32-bit contents of two registers * [A4]  10 * [A4] + 6 EXG A4,D2 ;preserve D2 MULU #10,D2 ;x10 ADD.L #6,D2 ;+6 EXG A4,D2 ;retreat D2 EXG SWAP SWAP Dn Exchanges the upper- and lower-order words of register Dn If [D1]=$1234567, after SWAP D1, [D1]=$45670123

  9. Position Independent Code LEA Table1(PC),A0 LEA Table2(PC),A1 MOVE.B #12,D0 Loop MOVE.B (A0)+,D1 ADD.B D1,(A1)+ SUB.B #1,D0 BNE Loop … Table1 DS.B 12 Table2 DS.B 12 Copy an effective address into an address register. LEA What does the code carry out?

  10. P1 DS.W 1 … PEA P1 BSR ABC LEA (4,SP),SP … ABC LEA (4,SP),A0 MOVEA.L (A0),A0 MOVE.W (A0),D0 … RTS A7 P1 A7 - 4 Return A7 - 8 P1 A7 - 8 Return P1 A0 Calculate an effective address and pushes it onto the stack. Parameter passing using the stack. PEA

  11. SP P SP P MOVE.W (SP)+,D0 ADD.W (SP)+,D0 MOVE.W D0,-(SP) Q Q SP P SP P Q P+Q NO direct memory-to-memory additions allowed ADD ADDI “ADDI.W #$1234,D4” and “ADD.W #$1234,D4” are equivalent But “ADDI #” can add to a memory location ADDI.W #$1234,(A0) Add an immediate value. ADDX Like ADD instruction, but also add X-bit. Used for extended arithmetic.

  12. ADDA ADDA.W #$8122,A0 Sign-extend $8122 to $FFFF8122 before add it to 32-bit A0. Compare to ADDA.L #$8122,A0 Machine codeAssembly code * ADDA.L and ADDA.W D1FC00000001 ADDA.L #1,A0 ;[A0] <- [A0] + 1 D0FC0001 ADDA.W #1,A0

  13. ADDQ.W #4,D1 Add a constant (1 to 8) to a memory location, or register. It is executed faster. Why is it faster than ADD.W #4,D1 Machine codeAssembly code * ADD and ADDQ 068000000009 ADD.L #9,D0 5080 ADD.L #8,D0 ;assembler changes ADD to ADDQ 5080 ADDQ.L #8,D0 06400009 ADD.W #9,D0 5040 ADD.W #8,D0 ;assembler changes ADD to ADDQ 5040 ADDQ.W #8,D0 ADDQ

  14. Clear a data register or memory location. Machine codeAssembly code * CLR and MOVE 7000 MOVEQ #0,D0 4280 CLR.L D0 303C0000 MOVE.W #0,D0 ;cannot use MOVEQ for word 4240 CLR.W D0 CLR

  15. DIVS, DIVU • DIVU: unsigned division • DIVS: signed division • Quotient (16 bits): in the lower 16 bits of a register • Remainder: in the upper 16 bits of a register • If [D0]=$00005678, after DIVU #$1234,D0, [D0]=$0DA80004 • How do we delete the remainder in D0? AND.L #$0000FFFF,D0 • How do we obtain the remainder? Use SWAP

  16. EXT • Sign extend. Often used with DIVS, because DIVS requires a 32-bit dividend. • EXT.L D1 sign-extends the low-order word in D1 to 32 bits by copying D1(15) to bits D1(16:31). MOVE.W (A0),D0 EXT.L D0 DIVS #42,D0 MOVE.W D0,2(A0) • EXT.W D1 sign-extends the low-order byte in D1 to 16 bits by copying D1(7) to bits D1(8:15).

  17. DIVU Example: GCD GCD(A,B) IF A < B THEN SWAP(A, B) WHILE ((R = (A MOD B)) != 0) DO A = B B = R GCD = B END

  18. ORG $400 CLR.L D0 MOVE.W A,D0 MOVE.W B,D1 CMP.W D1,D0 BGE NEXT MOVE.W D0,D2 MOVE.W D1,D0 MOVE.W D2,D1 NEXT EXT.L D0 DIVU D1,D0 SWAP D0 TST.W D0 BEQ DONE MOVE.W D0,D2 MOVE.W D1,D0 MOVE.W D2,D1 BRA NEXT DONE MOVE.W D1,GCD STOP #$2700 GCD or EXG D0,D1 ORG $1000 A DS.W 1 B DS.W 1 GCD DS.W 1 END $400

  19. MULS, MULU • MULS: multiply two 16-bit integers represented in 2’s complement. • MULU: multiply two 16-bit unsigned integers. • If [D1]=$ABCD5678 MULU.W #$1234,D1 Then [D1]=$6260060 as only low-order word of D1 is used in multiplication SUB, SUBA, SUBQ, SUBI, SUBX SUBI.B #$12,D1 [D0(0:7)]  [D0(0:7)] - $12

  20. NEG Calculate the 2’s complement of an operand MODULUS: TST.L D0 BPL Exit NEG.L D0 Exit RTS NEGX Calculate the 2’s complement of an operand minus the X-bit. Used for extended arithmetic.

  21. Logical Operations AND, OR, EOR, and NOT Example: A subroutine GetChar inputs an ASCII-encoded character, returns in D1 a 7-bit code plus a parity bit in the MSB. The following program will change a character to lower-case BSR GetChar ANDI.B #%01111111,D1 Clear MSB ORI.B #%00100000,D1 Set bit 5 • Note that: ‘A’ = 01000001 ‘a’ = 01100001 • How about lower-to-upper?

  22. Masking • Mask: bit pattern to isolate and manipulate some particular bits • To clear bits, use AND with 0s in the positions of bits to be cleared. • Example: Clear bits 2 and 5 in D0: AND.B #%11011011,D0

  23. Masking • To set bits, use OR with 1s in the positions of bits to be set. • Example: Set bits 1, 6, and 7 in D0: OR.B #%11000010,D0 • To invert bits, use EOR with 1s in the positions of bits to be inverted. • Example: Invert bits 0 and 1 in D0: EOR.B #%00000011,D0

  24. Shift Operations LSL, LSR, ASL, ASR LSL LSR 0 0 C Operand Operand C X X ASR ASL 0 MSB Operand C C Operand X X

  25. Rotate Operations (Circular shift) ROL, ROR ROL C Operand ROR C Operand Effect of shift and rotate operations (Table 5.1)

  26. CLR.B D1 ANDI.B #%01111111,D0 MOVE.B #7,D2 Next ROR.B #1,D0 ; [C] <- LSB of D0 BCC Zero ADDQ.B #1,D1 Zero SUB.B #1,D2 BNE Next ROR.B #1,D0 LSR.B #1,D1 ;Move LSB of D1 to C BCC Exit ORI.B #%10000000,D0 Exit ... Calculate the Even Parity Bit If the byte is P0110100, then P=1 to make the number of bit 1 in D0 even.

  27. Bit Operations BTST BTST #3,(A0) If the bit being tested is zero, then the Z-bit of CCR is set to 1. BSET BSET #3,(A0) Set the bit to 1 BCLR BCLR #3,(A0) Clear the bit to 0 BCHG BCHG #3,(A0) Invert the bit Example on Page 204

  28. Bit Operations We can implement bit operations using logical operations with masks. BTST #4,D0 AND.B #%00010000,D0 but D0 is destroyed BSET #4,D0 OR.B #%00010000, D0 BCLR #4,D0 AND.B #%11101111,D0 BCHG #4,D0 EOR.B #%00010000,D0

  29. Compare Instructions CMP, CMPA, CMPI, CMPM • The first operand is subtracted from the second, the result is NOT saved. • The content of the CCR is updated accordingly. • Special case: CMPM - compare memory location e.g.: CMPM (A1)+, (A2)+ • only post-incrementing is allowed w/ CMPM • useful for compare two tables

  30. BLOCK1 EQU <address1> BLOCK2 EQU <address2> SIZE EQU <# of words in block> LEA BLOCK1,A0 LEA BLOCK2,A1 MOVE.W #SIZE,D0 LOOP CMPM.W (A0)+,(A1)+ BNE NOT_SAME SUBQ.W #1,D0 BNE LOOP ALL_SAME … NOT_SAME ... Compare two blocks of memory for equality

  31. Conditional Branch: Bcc d8 or Bcc d16 where cc stands for condition code Branch takes a relative address. Why? Relative address is the address difference from current instruction to the instruction it branches to. d8 or d16 is in 2’s complement. d8 allows branching from -128 to 127. Numerical values for d8 or d16 are computed by assembler.

  32. MnemonicInstructionBranch on BCC, BHS (*) branch on carry clear BCS, BLO (*) branch on carry set BEQ branch on equal BGE branch on greater than or equal BGT branch on greater than BHI (*) branch on higher than BLE branch on less than or equal BLS (*) branch on lower than or equal BLT branch on less than BMI branch on minus BNE branch on not equal BPL branch on plus BVC branch on overflow clear BVS branch on overflow set (*) Used w/ unsigned arithmetic Conditional Branch

  33. Example: Assume [D0]=$C0. CMP.B #25,D0 CMP.B #25,D0 BGE NEXT BHS NEXT Will the branch be taken? • Example: MOVE.B #$40,D0 MOVE.B #$60,D1 ADD.B D0,D1 [D1]=$A0 BMI MINUS Will the branch be taken? Conditional Branch

  34. Char_Code := Hex_Val + $30 IF Char_Code > $39 THEN Char_Code := Char_Code + $07 3 A 33 3A > 39 3A + 7 = 41 Convert a Hex. to ASCII MOVE.B Hex_Val,D0 ADDI.B #$30,D0 CMPI.B #$39,D0 BLS.S EXIT ADDQ.B #$07,D0 EXIT MOVE.B D0,Char_Code

  35. CASE Test of CAES 1: Action1 CASE 2: Action2 CASE 3: Action3 END: Unconditional Branch BRA, JMP BRA uses relative address. JMP uses any addressing modes. CLR.L D0 LEA JMPTAB,A0 MOVE.B TEST,D0 ASL.L #2,D0 [D0] <- [D0]*4 MOVEA.L (A0,D0),A0 JMP (A0) … JMPTAB DC.L Action1 DC.L Action2 DC.L Action3 … Action1 … Code1 Action2 … Code2 Action3 … Code3 IF TEST=0 THEN Action1 ELSE IF TEST=1 THEN Action2 ELSE IF TEST=2 THEN Action3

  36. 1 * 2 * Program Switch.x68 3 * 4 5 00004000 ORG $4000 6 00004000 00004018 TAB: DC.L ACT1 7 00004004 00004020 DC.L ACT2 8 9 00004008 4280 CLR.L D0 10 0000400A 41F84000 LEA TAB,A0 11 0000400E 20700000 MOVEA.L (A0,D0),A0 12 00004012 4ED0 JMP (A0) 13 00004014 4E722700 EXIT: STOP #$2700 14 15 00004018 223C00008888 ACT1: MOVE.L #$8888,D1 16 0000401E 60F4 BRA EXIT 17 00004020 223C00001111 ACT2: MOVE.L #$1111,D1 18 00004026 60EC BRA EXIT 19 20 00004000 END $4000 Unconditional Branch

  37. IF D0(0:15) <0 OR D0(0:15) > [ea] THEN Trap to Operating System Set Byte Conditionally SEQ Flag If it is zero, set all bits of Flag to 1. SPL Flag If it is positive, set all bits of Flag to 1. Check Register against Bounds CHK <effective Address>,D0

  38. No Operation: NOP Has no effect on the CPU. Just advance the PC to the next instruction. Used to create a time delay. Can be used to do bust-wait Trap and Overflow: TRAPV If the overflow bit, V, is set, TRAPV instruction causes exception (trap) to the operating system. ADD.L D0,D4 TRAPV

  39. IF [M(ea)] = 0 THEN Z  1 IF [M(ea)] < 0 THEN N  1 [M(ea){7}]  1 Test and Set: TAS <ea> The TAS instruction is indivisible and can not be interrupted by another process. It facilitates the synchronization of processors in a multiprocessor system (semaphore to indicate a memory is used by another process).

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