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PC Architectures: PC History

PC Architectures: PC History

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PC Architectures: PC History

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  1. PC Architectures: PC History • What’s a PC? • A “PC” is a personal computer, but not every personal computer is a “PC” (e.g. Apple Mac) • PC used to be “IBM-compatible” ET4508_p8 (KR)

  2. PC Architectures: PC History • How come IBM’s PCs became a standard? • PC IP (Intellectual Property): • HW can only be protected through patents • PC based on standard components (8088, 8259, etc), and as such was not wholly patentable. • Anyone could easily copy PC hardware • SW (protected through copyrights) • BIOS:Originally written and owned by IBM. Reverse-engineered by Phoenix. Also available from AMI, Microid, etc. • DOS:IBM hired Microsoft to develop DOS. IBM failed to secure exclusive rights (“most costly business mistake in history”). Microsoft licensed DOS to PC cloners like Compaq, etc. ET4508_p8 (KR)

  3. PC Architectures: PC History • Who controls the PC standard today? • Who controls PC Software?MICROSOFT(Provides OS bundled with lots of SW. Applications) • Who controls PC Hardware?INTEL(No 1 manufacturer of processors, chipsets, motherboards)80% of all PC systems are based on Intel motherboards! • PCs are often called WINTEL systems... ET4508_p8 (KR)

  4. PC Architectures: PC History • A few PC History Milestones • 1971: Intel introduces 4004 processor • 1975: Altair 8800 (first commercial personal computer) • 1976: Apple I (sold for $666) • 1977: Apple II. Tandy TRS-80. Commodore PET. • 1978: Intel introduces 8086 • 1979: Motorola introduces 68000 • 1980: Seagate introduces first hard disk drive • 1981: IBM releases its first PC • 1984: Apple Macintosh. IBM PC AT. ET4508_p8 (KR)

  5. PC Architectures: PC History • Why have PCs been so successful? • open standardised architecture • expandable hardware(ports and expansion slots: ISA, PCI, PC-Card…) • multitude of hardware manufacturers(cost, performance, choice) • compatibility (between, and backwards) • (few) standardised operating systems ET4508_p8 (KR)

  6. PC Architectures: PC History • Todays PCs are backward-compatible with the original IBM PC design • Supporting legacy code • is important element of the success of the PC Architecture • places restrictions on PC designs • Current trend is to discontinue legacy systems (such as ISA bus) which are no longer required ET4508_p8 (KR)

  7. Early PCs • IBM PC (1981): • i8088 based, 4.77 MHz, 8-bit PC-bus,No hard disk – one or two floppies. • IBM PC/XT (1983): • Included a 10MB Hard Disk, and a better floppy  • Many PC and PC/XT Clones used the i8086 • IBM PC/AT (1984): • i80286 based • 6 MHz (first release) • 16-bit AT-bus (which later became the ISA Standard) ET4508_p8 (KR)

  8. IBM PC Brief History: Family Two Systems Industry ignored MicroChannel & developed EISA ET4508_p8 (KR)

  9. PC/XT & PC/AT We will look at the following elements of the early PC architectures: • PC/AT or ISA Bus Standard • Interrupt Handling • DMA Handling • Serial (COM) Port • Parallel (LPT) Port ET4508_p8 (KR)

  10. Early PC Processor Circuitry ET4508_p8 (KR)

  11. PC/XT: X-Bus and Support Circuitry ET4508_p8 (KR)

  12. PC/XT: RAM and I/O Bus Slots ET4508_p8 (KR)

  13. PC/AT: 80286 Processor Section ET4508_p8 (KR)

  14. PC/AT Support Circuitry ET4508_p8 (KR)

  15. PC/AT RAM Memory and I/O Bus Slots ET4508_p8 (KR)

  16. PC/AT Block Diagram ET4508_p8 (KR)

  17. PC/AT Bus Standards • The AT-Bus is a 16-bit (data) bus and is based on the 8-bit PC-Bus • The ISA (Industry Standard Architecture) standard formalised the AT-Bus (16-bit) standard as an industry standard, and this standard is commonly referred to as the 'ISA Bus' standard • A more advanced bus, the EISA bus (Enhanced Industry Standard Architecture) is a standard, which is upwards compatible to the ISA bus ET4508_p8 (KR)

  18. PC Bus (8-bit) ET4508_p8 (KR)

  19. ISA Bus Connector ET4508_p8 (KR)

  20. Multiple Interrupt Sources in the PC • A PC processor can receive interrupt requests form more than one source • System has to resolve two things: • Identify what device requested the interrupt • Prioritise Interrupts when two requests happen at the same time. ET4508_p8 (KR)

  21. Vectored Interrupts ET4508_p8 (KR)

  22. Priority Schemes • A priority encoder is used to prioritise interrupts, e.g. ET4508_p8 (KR)

  23. Prioritising Multiple Interrupt Sources ET4508_p8 (KR)

  24. Interrupts on the PC • PC uses i8259a Programmable Interrupt Controller: ancestor of APIC Note that this is an 8-bit device ET4508_p8 (KR)

  25. i8259A Block Diagram ET4508_p8 (KR)

  26. i8259A Interrupt Timing ET4508_p8 (KR)

  27. i8259a in the PC ET4508_p8 (KR)

  28. Cascading i8259As in the PC/AT The interrupt request signal of the slave 8259 is connected to IRQ2 of the master 8259. The master passes control signals to the slave via the connections CAS0..CAS2. ET4508_p8 (KR)

  29. PC/AT Interrupt Priorities Priority Use of PC/AT Interrupt Highest IRQ0 Timer 0 IRQ1 Keyboard IRQ2 From slave 8259  IRQ8 Real time clock IRQ9 * IRQ10 IRQ11 IRQ12 IRQ13 C0-processor IRQ14 Hard disk controller IRQ15 IRQ3 COM2 port IRQ4 COM1 port IRQ5 LPT2 IRQ6 Floppydisk controller Lowest IRQ7 LPT1   * IRQ9 interrupt is redirected to IRQ2 vector ET4508_p8 (KR)

  30. PC/AT Interrupt Vectors • I80x86: the interrupt vector table is at the bottom of the memory map • The table is 1024 (400h) bytes in size and can contain 256 vectors. Each vector location is 4 bytes long (segment:offset address) ET4508_p8 (KR)

  31. PC/AT interrupt sources • An interrupt can be triggered by: • Software (also called Exceptions) • Execution of INT instruction • some other internal event (e.g. division error)   • Hardware • Peripheral devices usually generate external interrupt requests as asynchronous events. ET4508_p8 (KR)

  32. PC/AT Hardware Interrupt ET4508_p8 (KR)

  33. PC/AT Hardware Interrupt(2) • The vector pointer is transmitted from the i8259A to the MPU on the second INTA pulse of the interrupt cycle: • Vector Pointer: A9 A8 A7 A6 A5 L3 L2 L1 • A9..A5: locates the position of the 32 byte area within the vector table. Each i8259 has a 32 byte area to hold the eight 4-byte vector addresses  • L3..L1: interrupt level (1 of 8) from the 8259  • The processor multiplies the vector pointer by 4 to form a 10-bit address • This is the starting byte of the vector 4 byte location. ET4508_p8 (KR)

  34. PC/AT Interrupt Vector Table ET4508_p8 (KR)

  35. Software Interrupts triggered from a program – INT X ET4508_p8 (KR)

  36. Direct Memory Access: DMA • DMA provides direct access to the memory while the processor is temporarily disabled • Allows data to be transferred between memory and I/O devices at a rate that is limited only by the speed of the memory components or I/O components • DMA used for e.g.: • Memory refresh (Dynamic RAM) • Magnetic/optical read/write operations • Video operations (e.g. screen refresh) ET4508_p8 (KR)

  37. Direct Memory Access: DMA • DMA Definitions • DMA ReadTransfers data from memory to I/O • DMA WriteTransfers data from I/O to memory ET4508_p8 (KR)

  38. DMA: i8237A • DMA Controller: i8237A • i8238A = special purpose microcontroller for high-speed data transfer between memory and I/O • Although i8237A may not appear as a discrete component in recent PCs, it’s still there… (integrated in chipsets, ISPC) ET4508_p8 (KR)

  39. DMA in the PC & PC/AT: i8237A • The i8237A has four independent DMA channels • Original PC/XT design had one i8237A for four DMA channels • PC/AT used two i8237As to provide 7 DMA channels • i8237A is programmable device and can be configured for single transfers, block transfers, Reads, Writes or Memory-to-Memory transfers  ET4508_p8 (KR)

  40. i8237A • i8237A allows byte addressing for 8-bit data transfers • In the PC/AT design, a contrived 16-bit transfer design is implemented using the i8237A  • i8237A uses a multiplexed address and data bus to reduce the device pin count. • DB0..DB7 lines contain the data bus along with the high byte of the 16-bit address bus. • An external latch is required to demultiplex the address lines ET4508_p8 (KR)

  41. i8237A Logic symbol ET4508_p8 (KR)

  42. i8237A Block Diagram ET4508_p8 (KR)

  43. How the PC uses the i8237A ET4508_p8 (KR)

  44. DMA read transfer using the i8237A ET4508_p8 (KR)

  45. DMA Address Tracking • The i8237A has four registers for tracking memory addresses during a DMA block • BASE ADDRESS REGISTER • BASE WORD COUNT REGISTER • CURRENT ADDRESS REGISTER • CURRENT WORD COUNT REGISTER ET4508_p8 (KR)

  46. DMA in the PC/XT ET4508_p8 (KR)

  47. Cascaded i8237As in the PC/AT DMA Cascadation ET4508_p8 (KR)

  48. PC/AT DMA Channel priorities • DMA channel 0 (DREQ0) has the highest priority • DMA channel 7 (DREQ7) has the lowest • Note, when a DMA transfer is in session, it cannot be 'interrupted' by another DMA request, even if the DMA request is made by a higher priority DMA channel. • The current DMA transfer session will be completed before the pending DMA request is accepted ET4508_p8 (KR)

  49. DMA Channels in the PC/AT DMA Priority Pre-defined 8-bit or Use in PC/AT 16-bit ____________________________________________________________ DREQ0 Highest Memory Refresh* 8-bits DREQ1 Not defined 8-bits DREQ2 Floppy Disk 8-bits DREQ3 Not defined 8-bits DREQ4 Cascade not used DREQ5 Not defined 16-bits DREQ6 Not defined 16-bits DREQ7 Lowest Not defined 16-bits ET4508_p8 (KR)

  50. PC/AT Parallel Port (1) • The parallel printer port on the PC/AT is referred to as an LPT (Line Printer) • Originally designed to support theCentronics parallel printer interface standard • The LPT port is often used to connect to a range of devices e.g. Dongle, A/D converter, D/A converter  • PC/AT typically allows up to four ports: LPT1 - LPT4 ET4508_p8 (KR)