Omar F. Mousa Professor: Scott Wakefield

1. Placement & Routing Omar F. Mousa Professor: Scott Wakefield

2. Preparation • # Setup for Cadence tool set cdk_dir = /projects/cadlab/cadence/local setenv CDS_SITE $cdk_dir #set cdk_dir = /projects/cadlab/cadence/ic #setenv CDS_SITE $cdk_dir setenv CDS /projects/cadlab/cadence setenv INSTDIR /projects/cadlab/cadence/ic setenv TOOLSDIR $INSTDIR/tools setenv ALGROPATH $TOOLSDIR/pcb/bin setenv FETPATH $TOOLSDIR/fet/bin setenv SPECCTRAPATH $TOOLSDIR/specctra/bin setenv DFIIPATH $TOOLSDIR/dfII/bin setenv CAD_ROOT /projects/cadlab/cadence setenv XL_ROOT /projects/fpmcm/ setenv cds_root /projects/cadlab/cadence #setenv CDS_INST_DIR /projects/cadlab/cadence/ic setenv USE_NCSU_CDK set path = ( ${path} ${CAD_ROOT}/ic/tools.sun4v/bin) set path = ( ${path} ${CAD_ROOT}/ic/tools.sun4v/dfII/bin) set path = ( ${path} ${CAD_ROOT}/ic/tools/dracula/bin) set path = ( ${path} ${CAD_ROOT}/ldv/tools/bin) set path = ( ${path} ${CAD_ROOT}/ldv/tools/verilog/bin) set path = ( ${path}

3. Preparation ${CAD_ROOT}/dsm_se53/tools.sun4v/dsm/bin) set path = ( ${path} ${CAD_ROOT}/ambit/BuildGates/v3.0.30/bin) set path = ( ${path} ${XL_ROOT}/msp/bin) set path = ( $ALGROPATH $SPECCTRAPATH $TOOLSDIR/bin $FETPATH $DFIIPATH $path ) # For LDV #setenv LD_LIBRARY_PATH /urs/openwin/lib:/usr/dt/lib:/projects/cadlab/cadence/l#dv/tools/lib setenv LD_LIBRARY_PATH /usr/lib:/usr/openwin/lib:/usr/dt/lib:/projects/cadlab/cadence/ic/tools/lib setenv LM_LICENSE_FILE /projects/cadlab/cadence/license.809a3775 setenv CDS_LIC_FILE /projects/cadlab/cadence/license.809a3775 alias sedsm 'sedsm -m=200 &'

4. Preparation • $gtar zcvf <filename>.tgz. • source cadence.rc before running Silicon ensembling (SE) • Create a directory called for example “hw5” and two subdirectory \hw5\work and hw5\tech • Unzip all the files in the technology directory. • Make sure you are inside directory the hw5 when you run seultra (executable).

5. Placement and Routing We are going to use SE from cadence to do the Placement and Routing, the command to start the tool is "seultra". • Importing lef file: • select file->import->LEF, specify the lef file name (tsmc*.lef)

6. Placement and Routing • The Import LEF (Library Exchange Format) form lets you specify one or more LEF files when creating or updating the library information in your design. You must complete this form; without loading and verifying a library database, you can not work on your design. • Filter - controls which file names will be displayed in the Directory and File List field. By default, the pattern is ''*.lef''. • Directory and File List - lets you search for the LEF file you want to import. • Selection - displays the currently selected path. If you know the complete path, you can type it in.

7. Placement and Routing • Report File - specifies the name of the report file. The software will check the library for potential problems and mark them as infos. These are listed in the report. If errors are found, you must correct them before you can load your netlist. The default report file name is .importlef.rpt. The browse button lets you change the directory in which the system will put the report. • Options - lets you specify features that affect importing LEF. • Clear Existing Design Data - deletes the current LEF database and replaces it with the data entered on this form. The default is off. • Case Sensitive Names - makes a file unimportable to LEF, if its case (upper or lower case) is different than the one stated. For example, if the file name stated is and this option was on, the file would not be imported. The default is off. • Variables Button - opens the Environment Variables form that contains variables affecting the behavior of the Import LEF form.

8. Import Verilog: • You will need import all your design files and the tsmc25.v. Specify the top level module name. • Change the vdd! to VDD, gnd! to VSS

11. Optimization

13. Importing Verilog Files Reads in a Verilog netlist, compares it to the existing layout, and changes the layout where there are differences. Verilog Source Files - specifies one or more UNIX file names containing a textual Verilog netlist that has been changed. Each Verilog module defined in the given files is analyzed, compiled into binary format, and saved into the specified output library. The files can also be selected from the file browser. Click the [...] button to open the file browser. Example: ~/myVlogDesign/*.v Verilog Top Module - specifies the top module name of a Verilog design hierarchy

14. Importing Verilog Files • Compiled Verilog Reference Libraries - specifies one or more library names. These libraries contain previously compiled Verilog modules that may be referenced or used in another part of the given design. Note that each library name must be separated from other library names by a space, as seen in the example. • The paths to these libraries must be specified in the cds.lib file. If the cds.lib file exists in the directory where you started the software, the libraries defined in that cds.lib will be listed as default, else the same default as the output library is used.

15. Definitions • Ground pins of the cells. Ground pins of the cells are identified by their USE GROUND attribute defined in LEF. After the ground pin is identified, the pin is then connected to the ground net with the same name as the pin. If none of the names match, use the first one specified in this list. • Logic 1 Net - specifies the net name to be used in the layout to represent logic/constant ''1'' found in the Verilog netlist. Note that this net name must also be one of the power nets listed in the Power Nets field on this form. The default is ''vdd!'' • Logic 0 Net - specifies the net name to be used in the layout to represent logic/constant ''0'' found in the Verilog netlist. Note that the logic 0 net must be one of the ground nets listed in the Ground Nets field on this form. The default is ''gnd!'' • Special Nets - specifies one or more net names to be created as DEF's SPECIAL NETS. Names must be separated by either a comma or a space. If none (leaving this field blank) are specified, only those nets listed as power and ground nets will be created as SPECIAL NETS.

16. Definitions • Design Data To Keep - lets you choose features that you want to keep. Choose to keep distribution cells, nets, original placements, EEQ models, and LEQ models. • Distribution Cells - specifies that you want to retain a cell added to the database, even though it does not appear in the ECO list. In your DEF file, distribution cells have an attribute of ''+DIST.'' • Distribution Nets - specifies that you want to keep nets added to the database, even if they do not appear in the ECO netlist. In your DEF file, distribution nets have an attribute of ''+DIST.'' • Original Placements - specifies that the ECO replaces the new model of the existing component at the original placement location. • EEQ Models - specifies that you want ECO to treat EEQ model substitutions as non-ECO operations. If you do not choose this option, ECO may substitute EEQ models for models specified in the new netlist.

17. Definitions • LEQ Models - specifies that you want ECO to treat LEQ model substitutions as non-ECO operations. If this is not selected, ECO may substitute LEQ models for models specified in the new netlist. • Timing Cells & Nets - lets you specify whether or not you want to retain a cell/net added to the database using the QPOPT, PBOPT, or CT-GEN command, even if they do not appear in the ECO list. These cells are called ''timing cells/nets'' and have the attribute + SOURCE TIMING in the DEF file. The default is to retain the timing cells/nets. • Constraints - lets you specify whether or not you want to retain the constraints (SBC or path-based) in the database. You should only retain the constraints if they are still valid after the ECO. If the ECO deletes cells appearing in the constraints, then this option should not be used. The default is not to retain the constraints. • Checkpoint Name - designates a reference point in the design for tracking netlist changes to the next ECO. The name must be unique. The default will automatically generate a checkpoint based on the design name. • Variables Button - opens the Environment Variables form containing variables affecting the behavior of the Import Verilog ECO form.

18. Floor_Planning Floor Planning: • Click the floorplan-> initialize floorplan. • Set the pin to core distance to 20.00 and row fill ratio. • Remember to set the "flip every other row". • You can estimate the result by clicking "calculate".

19. Floor_Planning

20. Floor_Planning

21. Floor_Planning • Allows you to control the die size and aspect ratio of your design, as well as letting you create core and I/O rows with either vertical or horizontal orientation. INITIALIZE FLOORPLAN does not place any cells. • Design Statistics - displays the specifications of your design Statistics shown are number of cells, IO pads, corner pads, blocks, IO pins, and nets. The area (in square microns) is shown for cells, blocks, IOs, and corner cells. • Die Size Constraint - lets you to control the die size of your design. Specify one of the following: aspect ratio, height, width, or fixed size. When one of the first 3 choices (aspect ratio, height, and width) is selected, height and/or width will be derived by Init FP.

22. Floor_Planning • Aspect Ratio - sets the desired width to height ratio for the design. The default is 1. • Width - lets you set the width you want for the chip. Init FP will then determine the height. • Height - lets you set the height you want for the chip. Init FP will then determine the width. • Fixed Size - sets both the width and the height for the chip. • I/O To Core Distance - specifies the distance between IO rows and the core area. • Left/Right - specifies the distance you want between the IO rows and the core area on the left and right side of your design. • Top/Bottom - specifies the distance you want between the IO rows and the core area on the top and bottom of your design.

23. Floor_Planning • Core Area Parameters - lets you to control the core area of your design. • Row Utilization (%) - specifies the target value for utilization of the core row. This is the ratio of the sum of the width of all cells to the effective sum of the length of all core rows, with the latter explained with this simple formula: • -(block+halo area) / (row height+row spacing)]= effective sum of the length of all core rows • Row Spacing - sets the amount of space between rows in the design. • Block Halo Per Side - sets the amount of space between the blocks and rows necessary for the routing of pins around blocks. You can set the value in microns or tracks. • Flip Every Other Row - lets you to flip every other core row in the design

24. Floor_Planning • Abut Rows - eliminates space between adjacent core rows. • Calculate - gives you feedback on the die size and row utilization resulting from the values you enter on this form, but doesn't commit you to creating the actual floorplan. Calculations displayed include the aspect ratio, core row utilization, chip area, IO to core distance, and the number of standard cells. • Variables Button - opens the Environment Variables form that contains variables relating only to the Initialize Floorplan form.

25. Placement • Click Placement -> cells, set the pin placement option and click place.

26. Placement • Placement - lets you choose the orientation for the added cell. Note that flipped orientations first turn the model over along its vertical axis and then rotate it. The default is that all orientations are allowed. Choose Preendcap or Postendcap and, in descending order of preference, choose North, East, South, West, Flipped North, Flipped East, Flipped South, or Flipped West. • Pin - specifies the pin name to connect. • Net - specifies the net that the pins are connected to. • Special Pin - specifies the special pins to connect. • Special Net - specifies the special nets that the pins are connected to. • Area - lets you pick the area where you want to add cells. To select, click the Area button and then click the part of the design you want to add cells to. The coordinates of that area will appear in the X1,X2, Y1, and Y2 fields on the form.

28. Placement

29. Placement This how it suppose to look like after Placement

30. Placement • Use the Place Optimization form to resolve timing, signal and design integrity, and scan chain violations after placement or clock tree generation. The form lets you specify the optimization operations allowed and the violations to be repaired without leaving the Envisia place-and-route environment. To optimize concurrently with placement, choose Place - Cells from the Envisia place-and-route menu and open the Place Optimization Options form. • Optimize: Timing - allows you to repair timing violations. During timing optimization, the software calls the Affirma® Pearl® timing analyzer to generate constraints.

31. Placement • Optimize: Signal Integrity - allows you to analyze and repair signal and design integrity violations. • Optimize: Scan Chains - allows you to detach the scan chain nets before each global placement pass and reconnect them afterward to minimize wirelength.

32. Placement • Resolve Violations - lets you specify the violations to be resolved during optimization and the operations to use to resolve them. If you select more than one of the Optimize options above, the software optimizes for all violations concurrently to ensure that it does not repair one kind of violation by creating another. • Setup - refers to the time before a clock edge when the data input must remain constant. It is defined in the TLF file. Setup-type checks involve upper bounds on signal arrival times. If you select setup, the software finds and corrects violations if the data input changes during the setup time.

33. Placement Hold - refers to the time after a clock edge when the data input must remain constant. It is defined in the TLF file. Hold-type checks involve lower bounds on signal arrival times.If you select hold, the software finds and corrects violations if the data input changes during the hold time. - Max Load - (maximum load) on a pin is the sum of the capacitances of all the pins on the net plus the capacitance of the net interconnect. It is defined in the TLF file. If you select max load, and the load on the pin is greater than the maximum load defined in the TLF, the software finds and corrects maximum load violations. - Max Transition - (maximum transition) is the time limit for an input or output pin to change from high to low or low to high. It is defined in the TLF file. If you select max transition, the software finds and corrects maximum transition violations when the time a pin takes to change exceeds the time limit defined in the TLF.

34. Placement • Hot electron - effect (also called hot carrier damage) is also a reliability problem. It refers to the damage high-velocity electrons can inflict on the gate/drain interface or the gate oxide interface, which can change the threshold and mobility of devices. To alleviate effects from hot electrons, the placer resizes drivers or inserts buffers. • Allowed Operations: - lets you specify the optimization operations allowed. • Insert buffers - allows buffers to be added to fix violations. Inserting buffers changes the netlist for the design.

35. Placement • Delete buffers - allows buffers to be removed to fix violations. Deleting buffers changes the netlist for the design. • Upsize cells - and downsize cells allow a core component to be replaced with a logically equivalent (LEQ) driver with a stronger or weaker drive strength. Two components are LEQ if they compute the same function, but have differing electrical characteristics, such as drive strengths, intrinsic delays, and so on. Pin geometries, obstructions, size, foreign references, orientation, power/grid connections, and site requirements can all differ among LEQ drivers. When a component is upsized or downsized, its model name is changed in the DEF file. • Optimization Report File - sets the name for the report generated by optimization. The default value for the name is design_name.qpopt.rpt.

36. Placement • Report File - shows the name of the timing analysis report. The default value for the filename is design_name.path. If you change the filename, keep the .path extension, because that is the extension other timing-related commands search for. Sets the Timing. • Variables - opens the Environment Variables form, which describes environment variables that relate to the Place Optimization form.

37. Adding Filler Select Placement -> Filler -> cell, specify the Filler cell name as "FILL16", or "FILL8", and so on, clear the "surfix" option. Keep adding cells till "FILL1". ** Un-button all east&west placement options **

38. Adding Filler • The PRoute Add Filler Cells form lets you add filler cells to your entire design or to a specified area, during special routing. New cells will have their pins assigned to the specified nets in the order you choose. • Model - specifies the name of the cell model to add. You must give a model name. • Prefix - sets the prefix of the set of cells you want to add initially, the cells to append to the existing placement, or the cells to delete. • Note that, if you want to add cells with new names, you must first specify a prefix. Then, a unique name using your prefix, a dash, and a number is created. Do not use a dash in your prefix. To append to previously added calls, you must specify a prefix that is different from existing cells. This prevents you from deleting the cells.

39. Adding Filler • Area - lets you pick the area where you want to add cells. To select, click the Area button and then click the part of the design you want to add cells to. The coordinates of that area will appear in the X1,X2, Y1, and Y2 fields on the form. • Variables Button - opens the Environment Variables form that contains only Add Filler Cells variables.

41. Adding Filler

42. Exporting Files You will need to export two files, DEF and GDSII In exporting GDSII file, set up the layer map file and the top level module name and the 'units' to 'thousands'.

43. Routing • There are three steps here, First is Plan power, at the pop up window, select add ring, set ring width 5.0 and place ring on IO side.

44. Routing • Step Two: • Close the pop-up window, and click on connect rings to finish the power routing. • Step Three: • Click on route in the routing menu, set options as "search and repair". • In option, select "minimize wire length". Click route to start the routing, this will take couple minutes.

47. Routing

48. Routing

49. Routing • The Power Planner (PP) Toolbox lets you select the forms available within the new Power Planner. Click the name of the form you want to open. NOTE: When you are in the Power Planner tool, many other menus on the user interface (such as entries under the File menu) may be greyed out. To access a greyed menu selection (re-enable it), exit the Power Planner area of the tool by clicking the Close button on this form. • Power Planner (PP) Add Rings - lets you put rings of wires around the core area and blocks in your design. • Power Planner (PP) Add Stripes - lets you add power stripes in designated clusters of your design or throughout the entire chip.

50. Routing • Power Planner (PP) Delete Stripes - allows you to delete all stripes in your design or stripes in a specified cluster. • Power Planner (PP) Add Ring Wire - lets you add a ring wire. • Power Planner (PP) Change Ring Wire - lets you edit the location, width, and spacing of a ring wire in your design. • Power Planner (PP) Delete Ring Wire - lets you delete a ring wire from your design. • Power Planner (PP) Delete Power Path - lets you delete a power path. This form should be used BEFORE you run the PP Add Rings form. • Power Planner (PP) Query Power Path - lets you get information about the nets and wires of a specified power path.