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Systolic Architectures

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Slides from Shaaban. Systolic Architectures. Replace single processor with an array of regular processing elements Orchestrate data flow for high throughput with less memory access. Different from pipelining

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Systolic Architectures

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  1. Slides from Shaaban Systolic Architectures • Replace single processor with an array of regular processing elements • Orchestrate data flow for high throughput with less memory access • Different from pipelining • Nonlinear array structure, multidirection data flow, each PE may have (small) local instruction and data memory • Different from SIMD: each PE may do something different • Initial motivation: VLSI enables inexpensive special-purpose chips • Represent algorithms directly by chips connected in regular pattern

  2. b2,2 b2,1 b1,2 b2,0 b1,1 b0,2 b1,0 b0,1 b0,0 a0,2 a0,1 a0,0 a1,2 a1,1 a1,0 a2,2 a2,1 a2,0 Systolic Array Example: 3x3 Systolic Array Matrix Multiplication • Processors arranged in a 2-D grid • Each processor accumulates one • element of the product Alignments in time Columns of B Rows of A T = 0 Example source: http://www.cs.hmc.edu/courses/2001/spring/cs156/

  3. b2,2 b2,1 b1,2 b2,0 b1,1 b0,2 b1,0 b0,1 a0,2 a0,1 a1,2 a1,1 a1,0 a2,2 a2,1 a2,0 Systolic Array Example: 3x3 Systolic Array Matrix Multiplication • Processors arranged in a 2-D grid • Each processor accumulates one • element of the product Alignments in time b0,0 a0,0*b0,0 a0,0 T = 1 Example source: http://www.cs.hmc.edu/courses/2001/spring/cs156/

  4. b2,2 b2,1 b1,2 b2,0 b1,1 b0,2 a0,2 a1,2 a1,1 a2,2 a2,1 a2,0 Systolic Array Example: 3x3 Systolic Array Matrix Multiplication • Processors arranged in a 2-D grid • Each processor accumulates one • element of the product Alignments in time b1,0 b0,1 a0,0*b0,0 + a0,1*b1,0 a0,0*b0,1 a0,0 a0,1 b0,0 a1,0*b0,0 a1,0 T = 2 Example source: http://www.cs.hmc.edu/courses/2001/spring/cs156/

  5. a1,2 a2,2 a2,1 Systolic Array Example: 3x3 Systolic Array Matrix Multiplication • Processors arranged in a 2-D grid • Each processor accumulates one • element of the product b2,2 b2,1 b1,2 Alignments in time b2,0 b0,2 b1,1 a0,0*b0,0 + a0,1*b1,0 + a0,2*b2,0 a0,0*b0,1 + a0,1*b1,1 a0,0 a0,1 a0,2 a0,0*b0,2 b0,1 b1,0 a1,0*b0,0 + a1,1*b1,0 a1,0 a1,1 a1,0*b0,1 b0,0 a2,0*b0,0 a2,0 T = 3 Example source: http://www.cs.hmc.edu/courses/2001/spring/cs156/

  6. Systolic Array Example: 3x3 Systolic Array Matrix Multiplication • Processors arranged in a 2-D grid • Each processor accumulates one • element of the product Alignments in time b2,2 b1,2 b2,1 a0,0*b0,0 + a0,1*b1,0 + a0,2*b2,0 a0,0*b0,1 + a0,1*b1,1 + a0,2*b2,1 a0,1 a0,2 a0,0*b0,2 + a0,1*b1,2 b1,1 b2,0 b0,2 a1,0*b0,0 + a1,1*b1,0 + a1,2*a2,0 a1,1 a2,2 a1,0 a1,0*b0,2 a1,2 a1,0*b0,1 +a1,1*b1,1 b0,1 b1,0 a2,0*b0,1 a2,0 a2,0*b0,0 + a2,1*b1,0 a2,1 a2,2 T = 4 Example source: http://www.cs.hmc.edu/courses/2001/spring/cs156/

  7. Systolic Array Example: 3x3 Systolic Array Matrix Multiplication • Processors arranged in a 2-D grid • Each processor accumulates one • element of the product Alignments in time b2,2 a0,0*b0,0 + a0,1*b1,0 + a0,2*b2,0 a0,0*b0,1 + a0,1*b1,1 + a0,2*b2,1 a0,2 a0,0*b0,2 + a0,1*b1,2 + a0,2*b2,2 b2,1 b1,2 a1,0*b0,0 + a1,1*b1,0 + a1,2*a2,0 a1,2 a1,1 a1,0*b0,2 + a1,1*b1,2 a1,0*b0,1 +a1,1*b1,1 + a1,2*b2,1 b1,1 b0,2 b2,0 a2,0*b0,1 + a2,1*b1,1 a2,0*b0,2 a2,0 a2,1 a2,0*b0,0 + a2,1*b1,0 + a2,2*b2,0 a2,2 T = 5 Example source: http://www.cs.hmc.edu/courses/2001/spring/cs156/

  8. Systolic Array Example: 3x3 Systolic Array Matrix Multiplication • Processors arranged in a 2-D grid • Each processor accumulates one • element of the product Alignments in time a0,0*b0,0 + a0,1*b1,0 + a0,2*b2,0 a0,0*b0,1 + a0,1*b1,1 + a0,2*b2,1 a0,0*b0,2 + a0,1*b1,2 + a0,2*b2,2 b2,2 a1,0*b0,0 + a1,1*b1,0 + a1,2*a2,0 a1,2 a1,0*b0,2 + a1,1*b1,2 + a1,2*b2,2 a1,0*b0,1 +a1,1*b1,1 + a1,2*b2,1 b2,1 b1,2 a2,0*b0,1 + a2,1*b1,1 + a2,2*b2,1 a2,0*b0,2 + a2,1*b1,2 a2,1 a2,2 a2,0*b0,0 + a2,1*b1,0 + a2,2*b2,0 T = 6 Example source: http://www.cs.hmc.edu/courses/2001/spring/cs156/

  9. Systolic Array Example: 3x3 Systolic Array Matrix Multiplication • Processors arranged in a 2-D grid • Each processor accumulates one • element of the product Alignments in time a0,0*b0,0 + a0,1*b1,0 + a0,2*b2,0 a0,0*b0,1 + a0,1*b1,1 + a0,2*b2,1 a0,0*b0,2 + a0,1*b1,2 + a0,2*b2,2 a1,0*b0,0 + a1,1*b1,0 + a1,2*a2,0 a1,0*b0,2 + a1,1*b1,2 + a1,2*b2,2 a1,0*b0,1 +a1,1*b1,1 + a1,2*b2,1 Done b2,2 a2,0*b0,1 + a2,1*b1,1 + a2,2*b2,1 a2,0*b0,2 + a2,1*b1,2 + a2,2*b2,2 a2,2 a2,0*b0,0 + a2,1*b1,0 + a2,2*b2,0 T = 7 Example source: http://www.cs.hmc.edu/courses/2001/spring/cs156/

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