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Advanced FPGA Design Principles: RocketIO in Xilinx FPGAs

This overview delves into the high-speed serial links design with Xilinx RocketIO in FPGAs, focusing on transceivers, pre-emphasis, equalization, clock recovery, and dynamic reconfiguration. Learn about the benefits of serial communication over parallel, FPGA's role in interfacing standards, and the challenges and applications of run-time reconfigurable hardware.

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Advanced FPGA Design Principles: RocketIO in Xilinx FPGAs

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  1. Xilinx RocketIO Nye FPGA egenskaper  (Max kap.21-22) Innhold: • Design med høyhastighets serielinker • Beregning med rekonfigurering av FPGA INF3430 - H13

  2. Parallell vs. seriekommunikasjon INF3430 - H13

  3. Differensielle ledningspar INF3430 - H13

  4. FPGA som grensesnitt mellom to standarder Figure 21-05 INF3430 - H13

  5. Forvrengning/demping av signal Figure 21-06 INF3430 - H13

  6. Sending av signal med etterfølgende like verdier Figure 21-07 INF3430 - H13

  7. Transceiver blokk Figure 21-08 INF3430 - H13

  8. Et antall transceiver blokker INF3430 - H13

  9. Konfigurerbare parametre Nødvendig pga forskjellige kommunikasjonsstandarder og for å oppnå høyest mulig datarate. • Differensielle signaler • Termineringsmotstander • ”Comma” tegn • Pre-emphasis • Utgjevning (equalization) INF3430 - H13

  10. Klokkegjenvinning Figure 21-12 INF3430 - H13

  11. Pre-emphasis Figure 21-10 INF3430 - H13

  12. Utgjevning Figure 21-11 INF3430 - H13

  13. Sampling av innkommende signal Figure 21-13 INF3430 - H13

  14. Klokkejitter Klokkejitter: Kortvarig avvik i signaltransisjoner (flanker) i forhold til ideelt tidspunkt. INF3430 - H13

  15. Øyediagram Figure 21-15 INF3430 - H13

  16. Noen spørsmål • Hvorfor er seriekommunikasjon bedre enn parallellkommunikasjon? • Mange inn/ut pinner kreves (og dermed mange ledningsbaner mellom enheter). • Vanskelig å oppfylle krav til lik lederlenge/impedans. • Begrenset lengde på forbindelse ved parallellkommunikasjon. • Må en håndtere serieformat i FPGAen? • Nei, transceiver blokk konverterer til parallelt format. • Hvorfor må en programmere parametre for serielinker? • Kommunikasjonsstandarder har forskjellige krav. • For å oppnå høyest mulig datarate. • Hvor samples det i en seriestrøm? • I senter av hvert bit. INF3430 - H13

  17. Rekonfigurering av FPGA (kap. 22) INF3430 - H13

  18. Dynamisk rekonfigurering av forbindelser Figure 22-02 INF3430 - H13

  19. Dynamisk rekonfigurering av FPGAVirtuell maskinvare Figure 22-03 INF3430 - H13

  20. Virtuell maskinvare • Er en type beregning medrekonfigurering av FPGA. • Individuelle deler av den virtuelle maskinvaren kan rekonfigureres dynamisk. • En krets basert på virtuell maskinvare kan utføre langt større oppgaver enn den tilsynelatende har logikk til. • Den kan også ha andre fordeler som raskere utføring og mindre effektforbruk. • Hovedutfordringen er lang rekonfigureringstid for dagens FPGAer. INF3430 - H13

  21. Run-Time Reconfigurable Hardware(Ikke pensum)October 25, 09:00 – 10:00Track 1FPGA-forum 2007 Jim Tørresen University of Oslo, Norway http://www.ifi.uio.no/~jimtoer jimtoer@ifi.uio.no

  22. FPGA based system RAM FPGA Processor FPGA FPGA for data processing Traditional system RAM FPGA Processor Configuration

  23. Performance comparison (Nallatech)

  24. Functions well suited to FPGAacceleration • Searching • Sorting • Signal processing • Audio/video/image manipulation • Encryption • Error correction • Coding/decoding • Network packet processing • Data analysis (oil, gas, finance)

  25. Processor versus FPGA Processor • SRAM program memory • Program loaded at startup • Complete program in internal or external memory • No swapping to other programs • Processor technology ~1985 • FPGA technology 2007! Program memory External program memory

  26. Content • What is reconfigurable computing? • Commercial reconfigurable devices • FPGA-based co-processor boards • FPGAs in high-performance computing • Research in reconfigurable computing

  27. Degrees of reconfigurable computing • Static: Configuration is never changed after product is shipped. • Upgrade: Configuration is changed from time to time for bug fix or functional upgrade. • Run-time: A set of configurations (multi-context) are available which the FPGA switch between at run-time.

  28. Run-time reconfiguration of FPGA

  29. Why apply run-time reconfigurable computing • Physical hardware is smaller than the reconfigurable logic resources required • Space reduction • Cost reduction • Power consumption reduced • Computational speedup • Incorporating new data/patterns realized in reconfigurable logic

  30. Run-time reconfiguration • Space/power/cost optimization: • Reconfigure for change in function, protocol, standard etc • Infrequent reconfiguration • Speed optimization: • Reconfigure within a function or task • Frequent reconfiguration

  31. Challenges of run-time reconfiguration • Long time required for reconfiguration. • Interfacing between modules and different configurations if they need to communicate. • Avoid the system from being inactive during reconfiguration. • Avoid failure in operation during reconfiguration. • Provide predictability for safety critical systems.

  32. Bitstream sizes for Virtex FPGAs [Sed06]

  33. Models of reconfiguration [Com02] • Full reconfiguration • Partial reconfiguration • Xilinx Virtex-2, Virtex 2Pro, Virtex-4/5 • Atmel AT40K, AT6000 series, FPSLIC • Multi-context devices • IPFlex • Elixent • NEC DRP

  34. Summary Why apply reconfigurable computing: • Space/power/cost optimization: • Reconfigure for change in function, protocol, standard etc • Infrequent reconfiguration • Speed optimization: • Frequent reconfiguration or infrequent reconfiguration • Incorporating new data/patterns realized in reconfigurable logic • Industry has started to apply reconfigurable computing.

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