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Dynamic scheduling

This presentation discusses dynamic scheduling in computer architecture, focusing on Tomasulo’s algorithm. It explores in-order and out-of-order execution, detailing the implementation of Tomasulo's technique in hardware. Key topics include handling data hazards like RAW, WAW, and WAR through register renaming and operand availability checks. The session includes live demos illustrating in-order execution with data hazards, out-of-order execution with split instruction decoding, and speculative execution with dynamic branch prediction. Learn how these concepts improve overall processing efficiency in modern CPUs.

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Dynamic scheduling

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  1. Dynamic scheduling Kosarev Nikolay MIPT Apr, 2010

  2. Agenda • In-order execution • Out-of-order execution. • Tomasulo’s algorithm • Implementation in hardware • Demo • Hardware speculation • Demo

  3. In-order execution Data hazards - RAW, WAW. No WAR. Pipeline DIV R1 = R2, R3 ADD R1 = R2, R4 SUB R6 = R1, R5 (but code has no sense) DIV R1 = R2, R3 ADD R9 = R1, R4 SUB R8 = R4, R5

  4. Out-of-order execution Split ID into 2 stages: Issue - IS Decode, check for structural hazards Read operands - RO Wait until no data hazards, read operands Pipeline Out-of-order execution implies out-of-order completion (WB) Hazards – RAW, WAW, WAR DIV R0 = R2, R4 ADD R6 = R0, R8 SUB R8 = R10, R14 MUL R6 = R10, R8

  5. Tomasulo’s algorithm How are data hazards avoided? RAW – wait for availability of operands WAR, WAW – register renaming(переименование регистров) DIV R0 = R2, R4 ADD A = R0, R8 ADD R9 = A, R1 SUB B = R10, R14 MUL R6 = R10, B DIV R0 = R2, R4 ADD R6 = R0, R8 ADD R9 = R6, R1 SUB R8 = R10, R14 MUL R6 = R10, R8

  6. Implementation in HW

  7. Demo LD F6 = R2, 2 LD F2 = R3, 4 MUL F0 = F2, F4 SUB F8 = F2, F6 DIV F10 = F0, F6 ADD F6 = F8, F2 Tomasulo's algorithm for dynamic scheduling

  8. Hardware speculation • Based on 3 key ideas: • Dynamic branch prediction • Speculative execution • Dynamic scheduling • Extra stage: instruction commit • New buffer: ROB (reorder buffer) Pipeline

  9. Hardware speculation

  10. Demo Reorder buffer

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